rs232_uart_1_wrapper_xst.prj

来自「基于FPGA的防火墙系统设计.rar」· PRJ 代码 · 共 9 行

VHDL common_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\common_v1_00_a/hdl/vhdl/pselect.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite.vhd
vhdl work ../hdl/rs232_uart_1_wrapper.vhd