plb_bram_if_cntlr_1_bram_wrapper_xst.prj

来自「基于FPGA的防火墙系统设计.rar」· PRJ 代码 · 共 3 行

VERILOG plb_bram_if_cntlr_1_bram_elaborate_v1_00_a C:\myproj2\firewall\myxps\hdl\elaborate\plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/verilog/plb_bram_if_cntlr_1_bram_elaborate.v
verilog work ../hdl/plb_bram_if_cntlr_1_bram_wrapper.v