system_xst.srp

基于FPGA的防火墙系统设计.rar

#      RAMB16_S2_S2                : 32
# Shift Registers                  : 64
#      SRL16                       : 45
#      SRL16E                      : 19
# Clock Buffers                    : 1
#      BUFG                        : 1
# IO Buffers                       : 17
#      IOBUF                       : 17
# DCMs                             : 1
#      DCM                         : 1
# Others                           : 1
#      PPC405                      : 1
=========================================================================
PACKER Warning: Lut plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/Addr_cntr_load_en1 driving carry plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/GEN_SLOW_MODE_BURSTXFER.I_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/I_MUXCY can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                    1622  out of  13696    11%  
 Number of Slice Flip Flops:          1554  out of  27392     5%  
 Number of 4 input LUTs:              2153  out of  27392     7%  
    Number used as logic:             1869
    Number used as Shift registers:     64
    Number used as RAMs:               220
 Number of IOs:                         72
 Number of bonded IOBs:                 17  out of    556     3%  
 Number of BRAMs:                       32  out of    136    23%  
 Number of GCLKs:                        1  out of     16     6%  
 Number of PPC405s:                      1  out of      2    50%  
 Number of DCMs:                         1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                  | Load  |
-----------------------------------+------------------------------------------------------------------------+-------+
sys_clk_pin                        | dcm_0/Using_Virtex.DCM_INST:CLK0                                       | 1761  |
fpga_0_net_gnd_1_pin               | NONE(plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_31)| 32    |
-----------------------------------+------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                            | Buffer(FF name)                                                                               | Load  |
--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+
rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_RX_FIFO(rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_RX_FIFO:Q)| NONE(rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/data_Exists_I)| 1     |
rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_TX_FIFO(rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_TX_FIFO:Q)| NONE(rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/data_Exists_I)| 1     |
opb/OPB_Rst(opb/opb/POR_FF_I:Q)                                                                                           | NONE(rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/enable_interrupts)                         | 36    |
myfirewall_0/myfirewall_0/USER_LOGIC_I/sys_rst_in_inv(myfirewall_0/myfirewall_0/USER_LOGIC_I/sys_rst_in_inv1_INV_0:O)     | NONE(myfirewall_0/myfirewall_0/USER_LOGIC_I/slv_reg3_15)                                      | 44    |
plb2opb/plb2opb/OPBside_reset_Read_inprog_negedge_regd(plb2opb/plb2opb/I_OPBside_reset_Read_inprog_negedge_regd:O)        | NONE(plb2opb/plb2opb/I_Read_inprog_negedge_Reg)                                               | 1     |
plb2opb/BGO_dcrDBus<31>(plb2opb/XST_GND:G)                                                                                | NONE(plb2opb/plb2opb/I_Read_inprog_negedge_Reg)                                               | 4     |
plb2opb/plb2opb/PLBside_reset_OPB_retry_onRd(plb2opb/plb2opb/I_B_side_Reg_CLR:O)                                          | NONE(plb2opb/plb2opb/I_A_side_Reg)                                                            | 1     |
plb2opb/plb2opb/PLBside_reset_OPB_timeout_onRd(plb2opb/plb2opb/I_OPB_timeout_side_Reg_CLR:O)                              | NONE(plb2opb/plb2opb/I_OPB_timeout_Reg)                                                       | 1     |
plb2opb/plb2opb/PLB_abort_regd_clear(plb2opb/plb2opb/I_PLB_abort_regd_clear:O)                                            | NONE(plb2opb/plb2opb/I_PLB_abort_Reg)                                                         | 1     |
--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 6.924ns (Maximum Frequency: 144.419MHz)
   Minimum input arrival time before clock: 1.418ns
   Maximum output required time after clock: 3.830ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'sys_clk_pin'
  Clock period: 6.924ns (frequency: 144.419MHz)
  Total number of paths / destination ports: 47631 / 5054
-------------------------------------------------------------------------
Delay:               6.924ns (Levels of Logic = 9)
  Source:            plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/PAValid (FF)
  Destination:       plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_2 (FF)
  Source Clock:      sys_clk_pin rising
  Destination Clock: sys_clk_pin rising

  Data Path: plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/PAValid to plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.370   0.658  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/PAValid (PLB_PAValid)
     end scope: 'plb'
     begin scope: 'plb2opb'
     LUT3:I0->O           13   0.275   0.540  plb2opb/PLB_PAValid_int1 (plb2opb/PLB_PAValid_int)
     LUT4:I2->O            2   0.275   0.476  plb2opb/PLB_IF_I/BGO_rearbitrate_i1 (plb2opb/BGO_rearbitrate_int)
     LUT3:I1->O            8   0.275   0.614  plb2opb/BGO_rearbitrate1 (BGO_rearbitrate)
     end scope: 'plb2opb'
     begin scope: 'plb'
     LUT2:I0->O            2   0.275   0.514  plb/I_PLB_SLAVE_ORS/REARB_OR/_or00001 (PLB_Srearbitrate)
     LUT4:I0->O            1   0.275   0.468  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2opb_rearb_en_SW0_SW0 (N587)
     LUT4:I0->O            5   0.275   0.446  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2opb_rearb_en (plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2opb_rearb_en)
     LUT4:I2->O            2   0.275   0.378  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/_or0000 (plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/_or0000)
     FDRS:R                    0.536          plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_2
    ----------------------------------------
    Total                      6.924ns (2.831ns logic, 4.093ns route)
                                       (40.9% logic, 59.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_pin'
  Total number of paths / destination ports: 31 / 31
-------------------------------------------------------------------------
Offset:              1.418ns (Levels of Logic = 2)
  Source:            fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> (PAD)
  Destination:       dipsws_4bit/dipsws_4bit/gpio_core_1/gpio_Data_In_3 (FF)
  Destination Clock: sys_clk_pin rising

  Data Path: fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> to dipsws_4bit/dipsws_4bit/gpio_core_1/gpio_Data_In_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   0.878   0.331  iobuf_7 (fpga_0_DIPSWs_4Bit_GPIO_IO_I<3>)
     begin scope: 'dipsws_4bit'
     FD:D                      0.208          dipsws_4bit/gpio_core_1/gpio_Data_In_3
    ----------------------------------------
    Total                      1.418ns (1.086ns logic, 0.331ns route)
                                       (76.6% logic, 23.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_pin'
  Total number of paths / destination ports: 41 / 37
-------------------------------------------------------------------------
Offset:              3.830ns (Levels of Logic = 4)
  Source:            ps2_ports/ps2_ports/ps2_I1/ps2_sie_I/Clkpd (FF)
  Destination:       fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin (PAD)
  Source Clock:      sys_clk_pin rising

  Data Path: ps2_ports/ps2_ports/ps2_I1/ps2_sie_I/Clkpd to fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.370   0.332  ps2_ports/ps2_I1/ps2_sie_I/Clkpd (Clkpd1)
     end scope: 'ps2_ports'
     begin scope: 'ps2_ports_io_adapter'
     INV:I->O              1   0.275   0.332  ps2_ports_io_adapter/ps2_mouse_clk_T1_INV_0 (ps2_mouse_clk_T)
     end scope: 'ps2_ports_io_adapter'
     IOBUF:T->IO               2.522          iobuf_13 (fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin)
    ----------------------------------------
    Total                      3.830ns (3.167ns logic, 0.663ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 806.75 / 807.83 s | Elapsed : 806.00 / 807.00 s
 
--> 

Total memory usage is 200768 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :   11 (   0 filtered)