xparameters.h

基于FPGA的防火墙系统设计.rar

/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/

#define STDIN_BASEADDRESS 0x40600000
#define STDOUT_BASEADDRESS 0x40600000

/******************************************************************/

/* Definitions for driver PLBARB */
#define XPAR_XPLBARB_NUM_INSTANCES 1

/* Definitions for peripheral PLB */
#define XPAR_PLB_BASEADDR 0x00000000
#define XPAR_PLB_HIGHADDR 0x00000000
#define XPAR_PLB_DEVICE_ID 0
#define XPAR_PLB_PLB_NUM_MASTERS 2


/******************************************************************/

/* Definitions for driver OPBARB */
#define XPAR_XOPBARB_NUM_INSTANCES 1

/* Definitions for peripheral OPB */
#define XPAR_OPB_BASEADDR 0xFFFFFFFF
#define XPAR_OPB_HIGHADDR 0x00000000
#define XPAR_OPB_DEVICE_ID 0
#define XPAR_OPB_NUM_MASTERS 1


/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral RS232_UART_1 */
#define XPAR_RS232_UART_1_BASEADDR 0x40600000
#define XPAR_RS232_UART_1_HIGHADDR 0x4060FFFF
#define XPAR_RS232_UART_1_DEVICE_ID 0
#define XPAR_RS232_UART_1_BAUDRATE 9600
#define XPAR_RS232_UART_1_USE_PARITY 0
#define XPAR_RS232_UART_1_ODD_PARITY 0
#define XPAR_RS232_UART_1_DATA_BITS 8


/******************************************************************/

/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 3

/* Definitions for peripheral LEDS_4BIT */
#define XPAR_LEDS_4BIT_BASEADDR 0x40000000
#define XPAR_LEDS_4BIT_HIGHADDR 0x4000FFFF
#define XPAR_LEDS_4BIT_DEVICE_ID 0
#define XPAR_LEDS_4BIT_INTERRUPT_PRESENT 0
#define XPAR_LEDS_4BIT_IS_DUAL 0


/* Definitions for peripheral DIPSWS_4BIT */
#define XPAR_DIPSWS_4BIT_BASEADDR 0x40020000
#define XPAR_DIPSWS_4BIT_HIGHADDR 0x4002FFFF
#define XPAR_DIPSWS_4BIT_DEVICE_ID 1
#define XPAR_DIPSWS_4BIT_INTERRUPT_PRESENT 0
#define XPAR_DIPSWS_4BIT_IS_DUAL 0


/* Definitions for peripheral PUSHBUTTONS_5BIT */
#define XPAR_PUSHBUTTONS_5BIT_BASEADDR 0x40040000
#define XPAR_PUSHBUTTONS_5BIT_HIGHADDR 0x4004FFFF
#define XPAR_PUSHBUTTONS_5BIT_DEVICE_ID 2
#define XPAR_PUSHBUTTONS_5BIT_INTERRUPT_PRESENT 0
#define XPAR_PUSHBUTTONS_5BIT_IS_DUAL 0


/******************************************************************/

/* Definitions for driver PS2_REF */
#define XPAR_XPS2_NUM_INSTANCES 1

/* Definitions for peripheral PS2_PORTS */
#define XPAR_PS2_PORTS_BASEADDR 0x7A400000
#define XPAR_PS2_PORTS_HIGHADDR 0x7A40FFFF
#define XPAR_PS2_PORTS_DEVICE_ID 0


/******************************************************************/


/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff0000
#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff


/******************************************************************/

#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000

/******************************************************************/

#define XPAR_MYFIREWALL_NUM_INSTANCES 1

/* Definitions for peripheral MYFIREWALL_0 */
#define XPAR_MYFIREWALL_0_DEVICE_ID 0
#define XPAR_MYFIREWALL_0_BASEADDR 0x40700000
#define XPAR_MYFIREWALL_0_HIGHADDR 0x4070FFFF