system.pcf

基于FPGA的防火墙系统设计.rar

        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[14].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[15].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[16].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[17].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[18].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[19].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[20].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[21].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[22].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[23].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[24].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[25].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[26].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[27].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[28].SRL_I/SRL16E"
        BEL
        "plb2opb/plb2opb/PLB_IF_I/OPB_ABUS_SRL_I/SRL_GENERATE[29].SRL_I/SRL16E"
        BEL "plb2opb/plb2opb/OPB_IF_I/Mshreg_rst_d2/SRL16E" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[7].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[6].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[5].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[4].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[3].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[2].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[1].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[0].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[3].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[2].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[1].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[0].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/data_Exists_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[7].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[6].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[5].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[4].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[3].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[2].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[1].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[0].SRL16E_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/Addr_Counters[3].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/Addr_Counters[2].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/Addr_Counters[1].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/Addr_Counters[0].FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/data_Exists_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Delay_16"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Mid_Start_Bit_SRL16"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[8].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[7].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[6].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[5].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[4].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[3].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[2].Rest_Bits.Others_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Serial_To_Parallel[1].First_Bit.First_Bit_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/previous_RX"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/running_0"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/rx_2"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/FIFO_Write"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/stop_Bit_Position"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/start_Edge_Detected_0"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/rx_1"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/DIV16_SRL16E"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/FDRE_I"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/serial_Data"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_sel_0"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_sel_1"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_sel_2"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/tx_DataBits"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/TX"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/fifo_Read"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/tx_Start"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_9"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_8"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_6"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_5"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_7"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_4"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_3"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_1"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_0"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/Count_2"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Baud_Rate_I/EN_16x_Baud"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[7].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[6].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[5].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[4].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[3].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[2].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[1].OPB_rdBus_FDRE"
        BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OPB_rdDBus_DFF[0].OPB_rdBus_FDRE"
        BEL "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/Frame_Error_DFF"
        BEL "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/OverRun_Error_DFF"
        BEL "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/uart_CS_1_DFF" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/xfer_Ack" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/opb_RNW_1" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_RX_FIFO" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/reset_TX_FIFO" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/uart_CS_2" BEL
        "rs232_uart_1/rs232_uart_1/OPB_UARTLITE_Core_I/enable_interrupts" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_be_s1_3" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_data_s1_28" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_data_s1_30" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_data_s1_31" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_data_s1_29" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/last_pw_xferack_d2" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/last_pw_xferack_d1" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/postedwrack_s2" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_d1_0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/last_xferack_d1_s0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_28" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_29" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_30" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/last_xferack_d1" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_rnw_s1" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s1_d2" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_addr_s1_29" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/new_pw_s0_d1_0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/cycle_active" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_s1_0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/opb_select_s0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/opb_rnw_s0" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_29" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s1_d1" BEL
        "leds_4bit/leds_4bit/gpio_core_1/READ_REG_GEN[3].READ_REG_FF_I" BEL
        "leds_4bit/leds_4bit/gpio_core_1/READ_REG_GEN[2].READ_REG_FF_I" BEL
        "leds_4bit/leds_4bit/gpio_core_1/READ_REG_GEN[1].READ_REG_FF_I" BEL
        "leds_4bit/leds_4bit/gpio_core_1/READ_REG_GEN[0].READ_REG_FF_I" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_xferAck_Reg" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_OE_1" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_OE_0" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_Data_Out_3" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_Data_Out_2" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_Data_Out_1" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_Data_Out_0" BEL
        "leds_4bit/leds_4bit/gpio_core_1/iGPIO_xferAck" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_OE_3" BEL
        "leds_4bit/leds_4bit/gpio_core_1/gpio_OE_2" BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/Mshreg_bus2ip_data_s1_29/SRL16E"
        BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/Mshreg_bus2ip_data_s1_31/SRL16E"
        BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/Mshreg_bus2ip_data_s1_30/SRL16E"
        BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/Mshreg_bus2ip_data_s1_28/SRL16E"
        BEL
        "leds_4bit/leds_4bit/OPB_IPIF_I/OPB_BAM_I/Mshreg_bus2ip_be_s1_3/SRL16E"
        BEL "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_be_s1_3" BEL
        "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/last_pw_xferack_d2" BEL
        "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/last_pw_xferack_d1" BEL
        "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/postedwrack_s2" BEL
        "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_d1_0"
        BEL "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/last_xferack_d1_s0"
        BEL "dipsws_4bit/dipsws_4bit/OPB_IPIF_I/OPB_BAM_I/bus2ip_cs_hit_s0_0"
        BEL "dipsws_4bit/dipsws_4b