system.pcf

基于FPGA的防火墙系统设计.rar

        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_22.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_23.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_24.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_25.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_26.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_27.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_28.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_29.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_30.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_31.A_pins<53>"
        PIN "ppc405_0/ppc405_0/PPC405_i_pins<172>" PIN
        "ppc405_0/ppc405_0/PPC405_i_pins<421>" PIN
        "ppc405_0/ppc405_0/PPC405_i_pins<172>" PIN
        "ppc405_0/ppc405_0/PPC405_i_pins<421>" BEL
        "reset_block/reset_block/EXT_LPF/asr_lpf_0" BEL
        "reset_block/reset_block/SEQ/chip_Reset_Req_d2" BEL
        "reset_block/reset_block/SEQ/system_Reset_Req_d2" BEL
        "reset_block/reset_block/Core_Reset_Req_d2" BEL
        "reset_block/reset_block/EXT_LPF/exr_d1" BEL
        "reset_block/reset_block/EXT_LPF/lpf_int" BEL
        "reset_block/reset_block/core_req_edge" BEL
        "reset_block/reset_block/Rstc405resetcore" BEL
        "reset_block/reset_block/EXT_LPF/exr_lpf_3" BEL
        "reset_block/reset_block/EXT_LPF/asr_lpf_3" BEL
        "reset_block/reset_block/EXT_LPF/exr_lpf_2" BEL
        "reset_block/reset_block/EXT_LPF/asr_lpf_2" BEL
        "reset_block/reset_block/EXT_LPF/exr_lpf_1" BEL
        "reset_block/reset_block/EXT_LPF/asr_lpf_1" BEL
        "reset_block/reset_block/EXT_LPF/exr_lpf_0" BEL
        "reset_block/reset_block/EXT_LPF/lpf_asr" BEL
        "reset_block/reset_block/EXT_LPF/lpf_exr" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_5" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_4" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_3" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_2" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_1" BEL
        "reset_block/reset_block/SEQ/SEQ_COUNTER/q_int_0" BEL
        "reset_block/reset_block/SEQ/chip_Reset_Req_d3" BEL
        "reset_block/reset_block/SEQ/system_Reset_Req_d3" BEL
        "reset_block/reset_block/SEQ/pr" BEL "reset_block/reset_block/SEQ/Sys"
        BEL "reset_block/reset_block/SEQ/bsr" BEL
        "reset_block/reset_block/SEQ/Chip" BEL
        "reset_block/reset_block/SEQ/seq_cnt_en" BEL
        "reset_block/reset_block/SEQ/sys_dec_1" BEL
        "reset_block/reset_block/SEQ/sys_dec_2" BEL
        "reset_block/reset_block/SEQ/sys_dec_0" BEL
        "reset_block/reset_block/SEQ/sys_edge" BEL
        "reset_block/reset_block/SEQ/ris_edge" BEL
        "reset_block/reset_block/SEQ/seq_clr" BEL
        "reset_block/reset_block/SEQ/bsr_dec_2" BEL
        "reset_block/reset_block/SEQ/bsr_dec_0" BEL
        "reset_block/reset_block/SEQ/chip_dec_1" BEL
        "reset_block/reset_block/SEQ/pr_dec_2" BEL
        "reset_block/reset_block/SEQ/chip_dec_2" BEL
        "reset_block/reset_block/SEQ/chip_dec_0" BEL
        "reset_block/reset_block/SEQ/pr_dec_1" BEL
        "reset_block/reset_block/SEQ/pr_dec_0" BEL
        "reset_block/reset_block/CORE_RESET/q_int_3" BEL
        "reset_block/reset_block/CORE_RESET/q_int_2" BEL
        "reset_block/reset_block/CORE_RESET/q_int_1" BEL
        "reset_block/reset_block/CORE_RESET/q_int_0" BEL
        "reset_block/reset_block/Core_Reset_Req_d3" BEL
        "reset_block/reset_block/Rstc405resetsys" BEL
        "reset_block/reset_block/Rstc405resetchip" BEL
        "reset_block/reset_block/Bus_Struct_Reset_0" BEL
        "reset_block/reset_block/core_cnt_en" BEL
        "reset_block/reset_block/EXT_LPF/POR_SRL_I/SRL16E" BEL
        "reset_block/reset_block/Mshreg_Core_Reset_Req_d2/SRL16E" BEL
        "reset_block/reset_block/SEQ/Mshreg_system_Reset_Req_d2/SRL16E" BEL
        "reset_block/reset_block/SEQ/Mshreg_chip_Reset_Req_d2/SRL16E" BEL
        "reset_block/reset_block/EXT_LPF/Mshreg_asr_lpf_0/SRL16E" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1_1"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd5"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd8"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd7"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd6"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd4"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd3"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd2"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FFd1"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_1"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_0"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Cnt_on_plb2opb_rearb_2"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/PAValid" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/SAValid" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriRdMasterRegReg_0"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriRdMasterRegReg_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbPriRdMasterReg_i_0"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbPriRdMasterReg_i_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_0"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbRdDBusBusyReg_i"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbWrDBusBusyReg_i"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecWrMasterReg_i_0"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecWrMasterReg_i_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbDisMReqReg_0" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbDisMReqReg_1" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecRdInProgReg_i" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecWrInProgReg_i" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecRdMasterReg_i_0" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/arbSecRdMasterReg_i_1" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_0" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_1" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_2" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_3" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_DACK_CNTR_I/cnt_0" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_DACK_CNTR_I/cnt_1" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_DACK_CNTR_I/cnt_2" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_DACK_CNTR_I/cnt_3" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/PLB_RNWRegReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtTimeOutReg_i" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtCompReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtLine4AccReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/PLB_RNWReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtSingleAccReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtLine16AccReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtLine8AccReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtDAckReg" BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0"
        BEL
        "plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1"
        BEL "plb/plb/I_PLB_ARBITER_LOGIC/arbreset_i" BEL "plb/plb/POR_FF2_I"
        BEL "plb/plb/POR_FF1_I" BEL "plb/plb/POR_SRL_I/SRL16E" BEL
        "opb/opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_0"
        BEL
        "opb/opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_1"
        BEL
        "opb/opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_2"
        BEL
        "opb/opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3"
        BEL
        "opb/opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout"
        BEL "opb/opb/POR_FF_I" BEL "opb/opb/POR_SRL_I/SRL16E" BEL
        "plb2opb/plb2opb/OPB_IF_I/rst_d2" BEL
        "plb2opb/plb2opb/PLB_IF_I/rcv_last_write_status" BEL
        "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/waddr_rclk_synced_0"
        BEL
        "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/waddr_rclk_synced_1"
        BEL "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/raddr_0"
        BEL "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/waddr_0"
        BEL "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/raddr_1"
        BEL "plb2opb/plb2opb/RCV_DATA_IF_I/ASYNC_CLK_GEN.ASYNC_FIFO_I/waddr_1"
        BEL "plb2opb/plb2opb/XFER_IF_I/wr_addr_0" BEL
        "plb2opb/plb2opb/XFER_IF_I/wr_addr_1" BEL
        "plb2opb/plb2opb/XFER_IF_I/wr_addr_2" BEL
        "plb2opb/plb2opb/XFER_IF_I/wr_addr_3" BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[71].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[68].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[67].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[66].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[65].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[64].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[62].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[61].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[60].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[59].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[58].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[57].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[56].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[55].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[54].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[53].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[52].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[51].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[50].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[49].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[48].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[47].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[46].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[45].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[44].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[43].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[42].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[41].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[40].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[39].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[38].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[37].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[36].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[35].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[34].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[33].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[32].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[31].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[30].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[29].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[28].RAM_FF_I"
        BEL
        "plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[27].RAM_FF_I"