📄 ns.lib
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*
*
* This file contains the next subcircuit(s):
*
* LF155/NS LF156/NS LF157/NS
* LF255/NS LF256/NS LF257/NS
* LF351/NS LF353/NS LF355/NS
* LF356/NS LF357/NS LF411/NS
* LF412/NS LF441A/NS LF441B/NS
* LF442A/NS LF442B/NS LF444A/NS
* LF444B/NS LF451/NS LF453/NS
* LM111/NS LM118/NS LM124/NS
* LM13600/NS LM13700/NS LM158/NS
* LM218/NS LM224/NS LM258/NS
* LM2902/NS LM2904/NS LM318/NS
* LM324/NS LM358/NS LM359/NS
* LM4250/NS LM6118/NS LM6121/NS
* LM6132A/NS LM6132B/NS LM6142A/NS
* LM6142B/NS LM6152A/NS LM6152B/NS
* LM6161/NS LM6162/NS LM6164/NS
* LM6165/NS LM6171A/NS LM6171B/NS
* LM6172/NS LM6181/NS LM6218/NS
* LM6261/NS LM6262/NS LM6264/NS
* LM6265/NS LM6310/NS LM6311/NS
* LM6317/NS LM6361/NS LM6362/NS
* LM6364/NS LM6365/NS LM7121/NS
* LM7131A/NS LM7131B/NS LM7171A/NS
* LM7171B/NS LM7301/NS LM741/NS
* LMC6001A/NS LMC6001B/NS LMC6022/NS
* LMC6024/NS LMC6032/NS LMC6034/NS
* LMC6035/NS LMC6036/NS LMC6041A/NS
* LMC6041B/NS LMC6042A/NS LMC6042B/NS
* LMC6044A/NS LMC6044B/NS LMC6061A/NS
* LMC6061B/NS LMC6062A/NS LMC6062B/NS
* LMC6064A/NS LMC6064B/NS LMC6081A/NS
* LMC6081B/NS LMC6082A/NS LMC6082B/NS
* LMC6084A/NS LMC6084B/NS LMC6462A/NS
* LMC6462B/NS LMC6464A/NS LMC6464B/NS
* LMC6482A/NS LMC6484A/NS LMC6492A/NS
* LMC6492B/NS LMC6494A/NS LMC6494B/NS
* LMC6572A/NS LMC6572B/NS LMC6574A/NS
* LMC6574B/NS LMC6582A/NS LMC6582B/NS
* LMC6584A/NS LMC6584B/NS LMC660A/NS
* LMC660B/NS LMC662A/NS LMC662/NS
* LMC6681A/NS LMC6681B/NS LMC6682A/NS
* LMC6682B/NS LMC6684A/NS LMC6684B/NS
* LMC6762A/NS LMC6762B/NS LMC6772A/NS
* LMC6772B/NS LMC6953/NS LMC7101A/NS
* LMC7101B/NS LMC7111A/NS LM7111B/NS
* LMC7211A/NS LMC7211B/NS LMC7215/NS
* LMC7221A/NS LMC7221B/NS LMC7225/NS
* LPC660A/NS LPC660B/NS LPC661A/NS
* LPC661B/NS LPC662A/NS LPC662B/NS
* LH4161/NS LH4162/NS LM607/NS
* LM627/NS LM637/NS LM6685/NS
*
*
*
*
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
* modeled by assuming the option GMIN=1TOhm. If a different (non-
* default) GMIN value is needed, users may recalculate as follows:
* Rin=(R1||GMIN+R2||GMIN), where R1=R2,
* to maintain a consistent Rin model.
*//////////////////////////////////////////////////////////
*LF155 Monolithic JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF155/NS 1 2 99 50 28
*
*Features:
*Low input bias current = 30pA
*Low input offset current = 3pA
*High input impedance = 1Tohm
*Low input offset voltage = 1mV
*NOTE:Asymetrical slew rate not modeled.
*Use default gm=1e12
****************INPUT STAGE**************
*
IOS 2 1 3P
*^Input offset current
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=20 MHz
C4 5 6 1.9894E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 1.65MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 3E-3 1
*Input offset voltage.^
R8 99 49 50K
R9 49 50 50K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.63
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA3 0 0 0 9.6796E7
G1 98 9 5 6 2E-3
R5 98 9 100MEG
VA3 9 11 0
*Fp1=23.7 HZ
C3 98 11 67.154P
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 530.52M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 9 1
VA8 26 27 0
R16 27 28 25
V5 28 25 -.1V
D4 25 9 DX
V4 24 28 -.1V
D3 9 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
* modeled by assuming the option GMIN=1TOhm. If a different (non-
* default) GMIN value is needed, users may recalculate as follows:
* Rin=(R1||GMIN+R2||GMIN), where R1=R2,
* to maintain a consistent Rin model.
*//////////////////////////////////////////////////////////
*LF156 Monolithic JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF156/NS 1 2 99 50 28
*
*Features:
*Low input bias current = 30pA
*Low input offset current = 3pA
*High input impedance = 1Tohm
*Low input offset voltage = 1mV
*
****************INPUT STAGE**************
*
IOS 2 1 3P
*^Input offset current
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=20 MHz
C4 5 6 1.9894E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 4.65MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 3E-3 1
*Input offset voltage.^
R8 99 49 50K
R9 49 50 50K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.63
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA3 0 0 0 1.5944E7
G1 98 9 5 6 2E-3
R5 98 9 100MEG
VA3 9 11 0
*Fp1=31.96 HZ
C3 98 11 49.9798P
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 530.52M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 9 1
VA8 26 27 0
R16 27 28 20
V5 28 25 -.25
D4 25 9 DX
V4 24 28 -.25
D3 9 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
* modeled by assuming the option GMIN=1TOhm. If a different (non-
* default) GMIN value is needed, users may recalculate as follows:
* Rin=(R1||GMIN+R2||GMIN), where R1=R2,
* to maintain a consistent Rin model.
*//////////////////////////////////////////////////////////
*LF157 Monolithic JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF157/NS 1 2 99 50 28
*
*Features:
*Low input bias current = 30pA
*Low input offset current = 3pA
*High input impedance = 1Tohm
*Low input offset voltage = 1mV
*
****************INPUT STAGE**************
*
IOS 2 1 3P
*^Input offset current
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=12 MHz
C4 5 6 3.31573E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 4.65MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 3E-3 1
*Input offset voltage.^
R8 99 49 50K
R9 49 50 50K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.63
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA3 0 0 0 8.1291E7
G1 98 9 5 6 2E-3
R5 98 9 100MEG
VA3 9 11 0
*Fp1=224 HZ
C3 98 11 7.10513P
*
***************POLE STAGE***************
*
*Fp3=42 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 8.3766E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 530.52M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 15 1
VA8 26 27 0
R16 27 28 25
V5 28 25 0.1V
D4 25 15 DX
V4 24 28 0.1V
D3 15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
* modeled by assuming the option GMIN=1TOhm. If a different (non-
* default) GMIN value is needed, users may recalculate as follows:
* Rin=(R1||GMIN+R2||GMIN), where R1=R2,
* to maintain a consistent Rin model.
*//////////////////////////////////////////////////////////
*LF255 Monolithic JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF255/NS 1 2 99 50 28
*
*Features:
*Low input bias current = 30pA
*Low input offset current = 3pA
*High input impedance = 1Tohm
*Low input offset voltage = 1mV
*NOTE:Asymetrical slew rate not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 3P
*^Input offset current
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=20 MHz
C4 5 6 1.9894E-13
*
***********COMMON MODE EFFECT***********
*
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