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R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
* LM13600 Dual Operational Transconductance Amplifier
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
*
* Amplifier Bias Input
* | Diode Bias
* | | Positive Input
* | | | Negative Input
* | | | | Output
* | | | | | Negative power supply
* | | | | | | Buffer Input
* | | | | | | | Buffer Output
* | | | | | | | | Positive power supply
* | | | | | | | | |
.SUBCKT LM13600/NS 1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Controlled impedance buffers.
* Wide supply range of +/-2V to +/-22V.
*
* Note: This model is single-pole in nature and over-estimates
* AC bandwidth and phase margin (stability) by over 2X.
* Although refinement may be possible in the future, please
* use benchtesting to finalize AC circuit design.
*
* Note: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
******************************************************
*
C1 6 4 4.8P
C2 3 6 4.8P
* Output capacitor
C3 5 6 6.26P
D1 2 4 DX
D2 2 3 DX
D3 11 21 DX
D4 21 22 DX
D5 1 26 DX
D6 26 27 DX
D7 5 29 DX
D8 28 5 DX
D10 31 25 DX
* Clamp for -CMR
D11 28 25 DX
* Ios source
F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
F2 11 5 V2 1.022
F3 25 6 V3 1.0
F4 5 6 V1 1.022
F5 30 6 V3 1.0
* Output impedance
F6 5 0 POLY(2) V3 V7 0 0 0 0 1
G1 0 33 5 0 .55E-3
I1 11 6 300U
Q1 24 32 31 QX1
Q2 23 3 31 QX2
Q3 11 7 30 QX1
Q4 11 30 8 QY
V1 22 24 0V
V2 22 23 0V
V3 27 6 0V
V4 11 29 1.4
V5 28 6 1.2
V6 4 32 0V
V7 33 0 0V
.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY NPN (IS=6E-15 BF=140)
.MODEL DX D (IS=5E-16)
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
* LM13700 Dual Operational Transconductance Amplifier
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
*
* Amplifier Bias Input
* | Diode Bias
* | | Positive Input
* | | | Negative Input
* | | | | Output
* | | | | | Negative power supply
* | | | | | | Buffer Input
* | | | | | | | Buffer Output
* | | | | | | | | Positive power supply
* | | | | | | | | |
.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Wide supply range of +/-2V to +/-22V.
*
* Note: This model is single-pole in nature and over-estimates
* AC bandwidth and phase margin (stability) by over 2X.
* Although refinement may be possible in the future, please
* use benchtesting to finalize AC circuit design.
*
* Note: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
******************************************************
*
C1 6 4 4.8P
C2 3 6 4.8P
* Output capacitor
C3 5 6 6.26P
D1 2 4 DX
D2 2 3 DX
D3 11 21 DX
D4 21 22 DX
D5 1 26 DX
D6 26 27 DX
D7 5 29 DX
D8 28 5 DX
D10 31 25 DX
* Clamp for -CMR
D11 28 25 DX
* Ios source
F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
F2 11 5 V2 1.022
F3 25 6 V3 1.0
F4 5 6 V1 1.022
* Output impedance
F5 5 0 POLY(2) V3 V7 0 0 0 0 1
G1 0 33 5 0 .55E-3
I1 11 6 300U
Q1 24 32 31 QX1
Q2 23 3 31 QX2
Q3 11 7 30 QZ
Q4 11 30 8 QY
V1 22 24 0V
V2 22 23 0V
V3 27 6 0V
V4 11 29 1.4
V5 28 6 1.2
V6 4 32 0V
V7 33 0 0V
.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY NPN (IS=6E-15 BF=50)
.MODEL QZ NPN (IS=5E-16 BF=266)
.MODEL DX D (IS=5E-16)
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
*//////////////////////////////////////////////////////////
*LM158 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM158/NS 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 2mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/2 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* *//////////////////////////////////////////////////////////
*LM224 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM224/NS 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 2mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 3N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
*//////////////////////////////////////////////////////////
*LM2902 QUAD OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM2902/NS 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 2mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
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