cs_slc.rpt

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RPT
723
字号
GCLR     : INPUT;
G/OE     : INPUT;
p00      : INPUT;
p01      : INPUT;
p02      : INPUT;
p03      : INPUT;
p04      : INPUT;
p05      : INPUT;
p06      : INPUT;
p07      : INPUT;
p10      : INPUT;
p11      : INPUT;
p12      : INPUT;
p13      : INPUT;
p14      : INPUT;
p15      : INPUT;
p16      : INPUT;
p17      : INPUT;
p20      : INPUT;
p21      : INPUT;
p22      : INPUT;
p23      : INPUT;
p24      : INPUT;
p25      : INPUT;
p26      : INPUT;
p27      : INPUT;
p32      : INPUT;
p33      : INPUT;
p34      : INPUT;
p35      : INPUT;
p37      : INPUT;

-- Node name is 'AAA' 
-- Equation name is 'AAA', location is LC080, type is output.
 AAA     = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC075 &  Q0;

-- Node name is 'p36' 
-- Equation name is 'p36', location is LC072, type is output.
 p36     = LCELL(!G/OE $  GND);

-- Node name is 'Q0' = '|LPM_COUNTER:1|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'Q0', type is output 
 Q0      = TFFE( VCC,  _LC068,  GCLR,  VCC,  VCC);

-- Node name is 'Q1' = '|LPM_COUNTER:1|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'Q1', type is output 
 Q1      = TFFE( Q0,  _LC068,  GCLR,  VCC,  VCC);

-- Node name is 'Q2' = '|LPM_COUNTER:1|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'Q2', type is output 
 Q2      = TFFE( _EQ002,  _LC068,  GCLR,  VCC,  VCC);
  _EQ002 =  Q0 &  Q1;

-- Node name is 'Q3' = '|LPM_COUNTER:1|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is 'Q3', type is output 
 Q3      = TFFE( _EQ003,  _LC068,  GCLR,  VCC,  VCC);
  _EQ003 =  Q0 &  Q1 &  Q2;

-- Node name is '|LPM_COUNTER:4|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC113', type is buried 
_LC113   = TFFE( VCC,  p35,  GCLR,  VCC,  VCC);

-- Node name is '|LPM_COUNTER:4|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC070', type is buried 
_LC070   = TFFE( _LC113,  p35,  GCLR,  VCC,  VCC);

-- Node name is '|LPM_COUNTER:4|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC071', type is buried 
_LC071   = TFFE( _EQ004,  p35,  GCLR,  VCC,  VCC);
  _EQ004 =  _LC070 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC073', type is buried 
_LC073   = TFFE( _EQ005,  p35,  GCLR,  VCC,  VCC);
  _EQ005 =  _LC070 &  _LC071 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs4' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC074', type is buried 
_LC074   = TFFE( _EQ006,  p35,  GCLR,  VCC,  VCC);
  _EQ006 =  _LC070 &  _LC071 &  _LC073 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs5' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC075', type is buried 
_LC075   = TFFE( _EQ007,  p35,  GCLR,  VCC,  VCC);
  _EQ007 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC076', type is buried 
_LC076   = TFFE( _EQ008,  p35,  GCLR,  VCC,  VCC);
  _EQ008 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC078', type is buried 
_LC078   = TFFE( _EQ009,  p35,  GCLR,  VCC,  VCC);
  _EQ009 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 &  _LC076 & 
              _LC113;

-- Node name is '|LPM_COUNTER:4|dffs8' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC079', type is buried 
_LC079   = TFFE( _EQ010,  p35,  GCLR,  VCC,  VCC);
  _EQ010 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 &  _LC076 & 
              _LC078 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs9' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC077', type is buried 
_LC077   = TFFE( _EQ011,  p35,  GCLR,  VCC,  VCC);
  _EQ011 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 &  _LC076 & 
              _LC078 &  _LC079 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs10' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC069', type is buried 
_LC069   = TFFE( _EQ012,  p35,  GCLR,  VCC,  VCC);
  _EQ012 =  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 &  _LC076 & 
              _LC077 &  _LC078 &  _LC079 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs11' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC067', type is buried 
_LC067   = TFFE( _EQ013,  p35,  GCLR,  VCC,  VCC);
  _EQ013 =  _LC069 &  _LC070 &  _LC071 &  _LC073 &  _LC074 &  _LC075 & 
              _LC076 &  _LC077 &  _LC078 &  _LC079 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs12' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC066', type is buried 
_LC066   = TFFE( _EQ014,  p35,  GCLR,  VCC,  VCC);
  _EQ014 =  _LC067 &  _LC069 &  _LC070 &  _LC071 &  _LC073 &  _LC074 & 
              _LC075 &  _LC076 &  _LC077 &  _LC078 &  _LC079 &  _LC113;

-- Node name is '|LPM_COUNTER:4|dffs13' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC065', type is buried 
_LC065   = TFFE( _EQ015,  p35,  GCLR,  VCC,  VCC);
  _EQ015 =  _LC066 &  _LC067 &  _LC069 &  _LC070 &  _LC071 &  _LC073 & 
              _LC074 &  _LC075 &  _LC076 &  _LC077 &  _LC078 &  _LC079 & 
              _LC113;

-- Node name is '|LPM_COUNTER:4|dffs14' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC068', type is buried 
_LC068   = TFFE( _EQ016,  p35,  GCLR,  VCC,  VCC);
  _EQ016 =  _LC065 &  _LC066 &  _LC067 &  _LC069 &  _LC070 &  _LC071 & 
              _LC073 &  _LC074 &  _LC075 &  _LC076 &  _LC077 &  _LC078 & 
              _LC079 &  _LC113;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      d:\dk\1508\cs_slc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:11
   --------------------------             --------
   Total Time                             00:00:16


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,421K

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