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📄 cs_slc.rpt

📁 单片机开发资料光盘-双龙-686M.zip
💻 RPT
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字号:
C:    LC33 - LC48     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
D:    LC49 - LC64     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
E:    LC65 - LC80    16/16(100%)   7/ 8( 87%)   0/16(  0%)  18/36( 50%) 
F:    LC81 - LC96     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
G:   LC97 - LC112     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
H:  LC113 - LC128     5/16( 31%)   4/ 8( 50%)   0/16(  0%)   6/36( 16%) 


Total dedicated input pins used:                 3/4      ( 75%)
Total I/O pins used:                            40/64     ( 62%)
Total logic cells used:                         21/128    ( 16%)
Total shareable expanders used:                  0/128    (  0%)
Total Turbo logic cells used:                   21/128    ( 16%)
Total shareable expanders not available (n/a):   0/128    (  0%)
Average fan-in:                                  8.14
Total fan-in:                                   171

Total input pins required:                      33
Total fast input logic cells required:           0
Total output pins required:                      6
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     21
Total flipflops required:                       19
Total product terms required:                   59
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/ 128   (  0%)



Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  83      -   -       INPUT               0      0   0    0    0    0    0  aaaa
  50   (75)  (E)      INPUT               0      0   0    0    0    0    0  ALE
   1      -   -       INPUT               0      0   0    0    0    4   15  GCLR
  84      -   -       INPUT               0      0   0    0    0    1    0  G/OE
  10    (6)  (A)      INPUT               0      0   0    0    0    0    0  p00
  11    (5)  (A)      INPUT               0      0   0    0    0    0    0  p01
  12    (3)  (A)      INPUT               0      0   0    0    0    0    0  p02
  15   (29)  (B)      INPUT               0      0   0    0    0    0    0  p03
  16   (27)  (B)      INPUT               0      0   0    0    0    0    0  p04
  17   (25)  (B)      INPUT               0      0   0    0    0    0    0  p05
  18   (24)  (B)      INPUT               0      0   0    0    0    0    0  p06
  20   (21)  (B)      INPUT               0      0   0    0    0    0    0  p07
  21   (19)  (B)      INPUT               0      0   0    0    0    0    0  p10
  22   (17)  (B)      INPUT               0      0   0    0    0    0    0  p11
  24   (46)  (C)      INPUT               0      0   0    0    0    0    0  p12
  25   (45)  (C)      INPUT               0      0   0    0    0    0    0  p13
  27   (43)  (C)      INPUT               0      0   0    0    0    0    0  p14
  28   (40)  (C)      INPUT               0      0   0    0    0    0    0  p15
  29   (38)  (C)      INPUT               0      0   0    0    0    0    0  p16
  30   (37)  (C)      INPUT               0      0   0    0    0    0    0  p17
  31   (35)  (C)      INPUT               0      0   0    0    0    0    0  p20
  33   (64)  (D)      INPUT               0      0   0    0    0    0    0  p21
  34   (61)  (D)      INPUT               0      0   0    0    0    0    0  p22
  35   (59)  (D)      INPUT               0      0   0    0    0    0    0  p23
  36   (57)  (D)      INPUT               0      0   0    0    0    0    0  p24
  37   (56)  (D)      INPUT               0      0   0    0    0    0    0  p25
  39   (53)  (D)      INPUT               0      0   0    0    0    0    0  p26
  40   (51)  (D)      INPUT               0      0   0    0    0    0    0  p27
  41   (49)  (D)      INPUT               0      0   0    0    0    0    0  p32
  44   (65)  (E)      INPUT               0      0   0    0    0    0    0  p33
  45   (67)  (E)      INPUT               0      0   0    0    0    0    0  p34
  46   (69)  (E)      INPUT               0      0   0    0    0    0   15  p35
  49   (73)  (E)      INPUT               0      0   0    0    0    0    0  p37


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  52     80    E     OUTPUT      t        0      0   0    0    2    0    0  AAA
  48     72    E     OUTPUT      t        0      0   0    1    0    0    0  p36
  79    125    H         FF      t        0      0   0    1    1    4    0  Q0
  77    123    H         FF      t        0      0   0    1    2    2    0  Q1
  76    120    H         FF      t        0      0   0    1    3    1    0  Q2
  75    118    H         FF      t        0      0   0    1    4    0    0  Q3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -    113    H       TFFE      t        0      0   0    2    0    0   14  |LPM_COUNTER:4|dffs0
   -     70    E       TFFE      t        0      0   0    2    1    0   13  |LPM_COUNTER:4|dffs1
   -     71    E       TFFE      t        0      0   0    2    2    0   12  |LPM_COUNTER:4|dffs2
 (49)    73    E       TFFE      t        0      0   0    2    3    0   11  |LPM_COUNTER:4|dffs3
   -     74    E       TFFE      t        0      0   0    2    4    0   10  |LPM_COUNTER:4|dffs4
 (50)    75    E       TFFE      t        0      0   0    2    5    1    9  |LPM_COUNTER:4|dffs5
   -     76    E       TFFE      t        0      0   0    2    6    0    8  |LPM_COUNTER:4|dffs6
   -     78    E       TFFE      t        0      0   0    2    7    0    7  |LPM_COUNTER:4|dffs7
   -     79    E       TFFE      t        0      0   0    2    8    0    6  |LPM_COUNTER:4|dffs8
 (51)    77    E       TFFE      t        0      0   0    2    9    0    5  |LPM_COUNTER:4|dffs9
 (46)    69    E       TFFE      t        0      0   0    2   10    0    4  |LPM_COUNTER:4|dffs10
 (45)    67    E       TFFE      t        0      0   0    2   11    0    3  |LPM_COUNTER:4|dffs11
   -     66    E       TFFE      t        0      0   0    2   12    0    2  |LPM_COUNTER:4|dffs12
 (44)    65    E       TFFE      t        0      0   0    2   13    0    1  |LPM_COUNTER:4|dffs13
   -     68    E       TFFE      t        0      0   0    2   14    4    0  |LPM_COUNTER:4|dffs14


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC80 AAA
        | +----------------------------- LC70 |LPM_COUNTER:4|dffs1
        | | +--------------------------- LC71 |LPM_COUNTER:4|dffs2
        | | | +------------------------- LC73 |LPM_COUNTER:4|dffs3
        | | | | +----------------------- LC74 |LPM_COUNTER:4|dffs4
        | | | | | +--------------------- LC75 |LPM_COUNTER:4|dffs5
        | | | | | | +------------------- LC76 |LPM_COUNTER:4|dffs6
        | | | | | | | +----------------- LC78 |LPM_COUNTER:4|dffs7
        | | | | | | | | +--------------- LC79 |LPM_COUNTER:4|dffs8
        | | | | | | | | | +------------- LC77 |LPM_COUNTER:4|dffs9
        | | | | | | | | | | +----------- LC69 |LPM_COUNTER:4|dffs10
        | | | | | | | | | | | +--------- LC67 |LPM_COUNTER:4|dffs11
        | | | | | | | | | | | | +------- LC66 |LPM_COUNTER:4|dffs12
        | | | | | | | | | | | | | +----- LC65 |LPM_COUNTER:4|dffs13
        | | | | | | | | | | | | | | +--- LC68 |LPM_COUNTER:4|dffs14
        | | | | | | | | | | | | | | | +- LC72 p36
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC70 -> - * * * * * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs1
LC71 -> - - * * * * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs2
LC73 -> - - - * * * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs3
LC74 -> - - - - * * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs4
LC75 -> * - - - - * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs5
LC76 -> - - - - - - * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs6
LC78 -> - - - - - - - * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs7
LC79 -> - - - - - - - - * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs8
LC77 -> - - - - - - - - - * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs9
LC69 -> - - - - - - - - - - * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs10
LC67 -> - - - - - - - - - - - * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs11
LC66 -> - - - - - - - - - - - - * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs12
LC65 -> - - - - - - - - - - - - - * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs13

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- aaaa
1    -> - * * * * * * * * * * * * * * - | - - - - * - - * | <-- GCLR
84   -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- G/OE
46   -> - * * * * * * * * * * * * * * - | - - - - * - - * | <-- p35
LC113-> - * * * * * * * * * * * * * * - | - - - - * - - - | <-- |LPM_COUNTER:4|dffs0
LC125-> * - - - - - - - - - - - - - - - | - - - - * - - * | <-- Q0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                   Logic cells placed in LAB 'H'
        +--------- LC113 |LPM_COUNTER:4|dffs0
        | +------- LC125 Q0
        | | +----- LC123 Q1
        | | | +--- LC120 Q2
        | | | | +- LC118 Q3
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'H'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC125-> - * * * * | - - - - * - - * | <-- Q0
LC123-> - - * * * | - - - - - - - * | <-- Q1
LC120-> - - - * * | - - - - - - - * | <-- Q2

Pin
83   -> - - - - - | - - - - - - - - | <-- aaaa
1    -> * * * * * | - - - - * - - * | <-- GCLR
84   -> - - - - - | - - - - * - - - | <-- G/OE
46   -> * - - - - | - - - - * - - * | <-- p35
LC68 -> - * * * * | - - - - - - - * | <-- |LPM_COUNTER:4|dffs14


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             d:\dk\1508\cs_slc.rpt
cs_slc

** EQUATIONS **

aaaa     : INPUT;
ALE      : INPUT;

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