sport0_i2s_rx_isr.asm

电子元件资料-170M-pdf版.zip

/* **************************************************************************************************

				    		SPORT0 I2S RX INTERRUPT SERVICE ROUTINE

Receives loopback data from SPORT0 I2S TX pins via SPORT0 I2S RX and then sends the audio data back 
out to the AD1819A Stereo DACs/Line Outputs
			
***************************************************************************************************** 

   Serial Port 1 Transmit Interrupt Service Routine performs arithmetic computations on SPORT1 receive 
   data buffer (rx_buf) and sends results to SPORT1 transmit data buffer (tx_buf) 			     		
										     		
 i2s_rx_buf[2] - DSP SPORT0 I2S recieve buffer
 channel Description                         	DSP Data Memory Address
 ------  --------------------------------------	-------------------------------------------------
 0	 	 I2S Left Channel Data					DM(i2s_rx_buf + 0) = DM(i2s_rx_buf + LEFT) 
 1       I2S Right Channel Data   				DM(i2s_rx_buf + 1) = DM(i2s_rx_buf + RIGHT)


 i2s_tx_buf[2] - DSP SPORT0 I2S transmit buffer
 channel # Description                   		DSP Data Memory Address
 ------  -------------------------------------- --------------------------------------------------
 0	 	 I2S Left Channel TX Data				DM(i2s_tx_buf + 0) = DM(i2s_tx_buf + TAG_PHASE) 
 1       I2S Right Channel TX Data   			DM(i2s_tx_buf + 1) = DM(i2s_rx_buf + COMMAND_ADDRESS_SLOT) 

*****************************************************************************************************/

/* ADSP-21065L System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"

/* AD1819 SPORT0 Rx and Tx Timeslot Definitions */
#define		LEFT			0
#define		RIGHT			1

.GLOBAL		Process_AKM_I2S_Stereo_Data;
.GLOBAL 	Left_ChannelA_In;
.GLOBAL 	Right_ChannelA_In;
.GLOBAL		Left_ChannelA_Out;
.GLOBAL		Right_ChannelA_Out;
.GLOBAL 	Left_ChannelB_In;
.GLOBAL 	Right_ChannelB_In;
.GLOBAL		Left_ChannelB_Out;
.GLOBAL		Right_ChannelB_Out;
.EXTERN		rx0a_buf;
.EXTERN		tx0a_buf;
.EXTERN		rx0b_buf;
.EXTERN		tx0b_buf;
.EXTERN		Auto_Double_Tracking;

.segment /dm    dm_data;

/* stereo-channel data holders - used for DSP processing of audio data */
.VAR 		Left_ChannelA_In;
.VAR 		Right_ChannelA_In;
.VAR 		Left_ChannelB_In;
.VAR 		Right_ChannelB_In;

.VAR		Left_ChannelA_Out;
.VAR		Right_ChannelA_Out;
.VAR		Left_ChannelB_Out;
.VAR		Right_ChannelB_Out;

.VAR		I2S_timer = 0x00000000;

.endseg;

.segment /pm pm_code;

Process_AKM_I2S_Stereo_Data:
	bit set mode1 SRRFL;				/* enable secondary registers R0-R7 */
	nop;								/* 1 cycle latency writing to Mode1 register */

get_ADC_i2s_rx_data:	
	/* Get SPORT0 I2S channelA ADC data */
    r0 = dm(rx0a_buf + LEFT);       	/* Get i2s left channel rx data */
	r0 = lshift r0 by 8;   				/* shift up to MSBs to preserve sign */
    r1 = dm(rx0a_buf + RIGHT);      	/* Get i2s right channel rx data */
	r1 = lshift r1 by 8;   				/* shift up to MSBs to preserve sign */
	/* save for audio processing */
   	dm(Left_ChannelA_In) = r0;			
	dm(Right_ChannelA_In) = r1;

	/* Get SPORT0 I2S channelB ADC data */
	r0 = dm(rx0b_buf + LEFT);       	/* Get i2s left channel rx data */
	r0 = lshift r0 by 8;   				/* shift up to MSBs to preserve sign */
    r1 = dm(rx0b_buf + RIGHT);      	/* Get i2s right channel rx data */
	r1 = lshift r1 by 8;   				/* shift up to MSBs to preserve sign */
	dm(Left_ChannelB_In) = r0;			
	dm(Right_ChannelB_In) = r1;
	/* loop-back unaltered ADC data */
	dm(Left_ChannelB_Out) = r0;			
	dm(Right_ChannelB_Out) = r1;

/* --------------------------------------------------------------------------------------------	*/
/* 	user_applic( ) - User Applications Routines	                                                */
/* 	*** Insert DSP Algorithms Here ***                                                          */
/*                                                                                              */
/* 	Input L/R Data Streams - DM(Left_Channel_In) DM(Right_Channel_In)                           */
/* 	Output L/R Results     - DM(Left_Channel_Out) DM(Right_Channel_Out)                         */
/*                                                                                              */
/*	These left/right data holders are used to pipeline data through	multiple modules, and       */
/*	can be removed if the dsp programmer needs to save instruction cycles                       */
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~       */
/* 	Coding TIP:                                                                                 */
/*	The samples from the AKM ADCs are 24-bit and are in the lower 24 bits of the the 32-bit 	*/
/*	word.  They are shifted to the most significant bit positions in order to preserve the      */
/*	sign of the samples when they are converted to floating point numbers. The values are       */
/*	also scaled to the range +/-1.0 with the integer to float conversion                        */
/*	(f0 = float r0 by r1).                                                                      */
/*                                                                                              */
/*	To convert between our assumed 1.31 fractional number and IEEE floating point math,         */
/*	here are some example assembly instructions ...                                             */
/*                                                                                              */
/*		r1 = -31     <-- scale the sample to the range of +/-1.0                                */
/*		r0 = DM(Left_Channel);                                                                  */
/*   	f0 = float r0 by r1;                                                                    */
/*		[Call Floating_Point_Algorithm]                                                         */
/*    	r1 = 31;       <-- scale the result back up to MSBs                                     */   
/* 		r8 = fix f8 by r1;                                                                      */
/*		DM(Left_Channel) = r8;                                                                  */
/* -------------------------------------------------------------------------------------------- */

user_applic:
	call (pc, Auto_Double_Tracking);

	/* ---- DSP processing is finished, now playback results to DACs ---- */

	
tx_audio_data_out_I2S:
	/* transmit channel A audio data out of SPORT0 i2s port tx0A pins */
	{r0 = dm(i1,m1);}  					/* get sine data from 4K lookup table */
	{r1 = dm(i2,m2);} 					/* get sine data from 4K lookup table */
	r0 = dm(Left_ChannelA_Out); 		/* get Left Audio channel data */
	r1 = dm(Right_ChannelA_Out); 		/* get Right Audio channel data */
	r0 = lshift r0 by -8;				/* put back in bits 0..23 for SPORT tx */
	r1 = lshift r1 by -8;				/* put back in bits 0..23 for SPORT tx */
	dm(tx0a_buf + LEFT) = r0;			/* send i2s left channel tx data */
	dm(tx0a_buf + RIGHT) = r1;			/* send i2s right channel tx data */

	/* transmit channel B audio data out of SPORT0 i2s port tx0A pins */
	r0 = dm(Left_ChannelB_Out); 		/* get Left ADC channel data */
	r0 = lshift r0 by -8;				/* put back in bits 0..23 for SPORT tx */
	r1 = dm(Right_ChannelB_Out); 		/* get Right ADC channel data */
	r1 = lshift r1 by -8;				/* put back in bits 0..23 for SPORT tx */
	dm(tx0b_buf + LEFT) = r0;			/* send i2s left channel tx data */
	dm(tx0b_buf + RIGHT) = r1;			/* send i2s right channel tx data */


i2s_tx_done:
	r0=dm(I2S_timer);					/* get last count */
	r0=r0+1;							/* increment count */
	dm(I2S_timer)=r0;					/* save updated count */

	rti(db);							/* return from interrupt, delayed branch */
	bit clr mode1 SRRFL;				/* restore primary registers R0-R7 */
	nop;								/* 1 cycle latency writing to MODE1 register */

/* ----------------------------------------------------------------------------------------- */ 

.endseg;