sport0_i2smode_init.asm

电子元件资料-170M-pdf版.zip

/* ********************************************************************************************** */
/*	SPORT0 I2S Mode Initialization                                                                */
/*                                                                                                */
/*	These assembly routines set up the ADSP-21065L SPORT0 registers for I2S mode for              */ 
/*	transmitting and recieving of data in slave mode at 96 KHz.   								  */					
/*                                                                                                */
/*                                                                      By: John Tomarakos        */
/*                                                                      ADI DSP Applications      */
/*                                                                      Rev 1.0, 1/27/98          */
/*                                                                                                */
/* ********************************************************************************************** */

/* ADSP-21065L System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"

.GLOBAL	 	Program_DMA_Controller_SPT0;
.GLOBAL		Program_I2Smode_SPORT0_Registers;
.GLOBAL		rx0a_buf;
.GLOBAL		tx0a_buf;
.GLOBAL		rx0b_buf;
.GLOBAL		tx0b_buf;

.segment /dm    dm_I2S;

/* define buffer size to match I2S TDM stereo channels */
#define		STEREO_LR	2

#define		ID2			0x00000200		/* SYSTAT bit mask for SHARC B with ID = 2 */

.var rx0a_buf[STEREO_LR]; 	/* stereo I2S primary receive a buffer */
.var rx0b_buf[STEREO_LR]; 	/* stereo I2S secondary receive b buffer */				 
.var tx0a_buf[STEREO_LR];	/* stereo I2S primary transmit a buffer */		 
.var tx0b_buf[STEREO_LR];	/* stereo I2S secondary transmit b buffer */			
						
.var rcv0a_tcb[8]  = 0, 0, 0, 0, 0, 2, 1, 0;      /* receive a tcb */
.var rcv0b_tcb[8]  = 0, 0, 0, 0, 0, 2, 1, 0;      /* receive b tcb */
.var xmit0a_tcb[8] = 0, 0, 0, 0, 0, 2, 1, 0;      /* transmit a tcb */
.var xmit0b_tcb[8] = 0, 0, 0, 0, 0, 2, 1, 0;      /* transmit b tcb */

.endseg;

.segment /pm	pm_code;

/* ---------------------------------------------------------------------------------------------*/
/* Sport0 Control Register Programming 							  								*/
/* I'squared'S Mode dma w/ chain, slave mode, no pack, data=24/big/zero 						*/
/* ---------------------------------------------------------------------------------------------*/

Program_I2Smode_SPORT0_Registers:
	/* check if the DSP has ID = 2, If ID=2, then clear flag1 */
	/* This will activate a direct connection between that processor, and the AKM ADCs and DACs */
	R0 = dm(SYSTAT);
	R1 = ID2;
	R0 = R0 AND R1;
	IF EQ jump set_spt_regs;/* if ID=1, keep flag0 set, enables SPORT to SHARC A */	
	bit clr astat FLG1; 	/* clr flag 0 LED, enables SPORT to SHARC B */

set_spt_regs:
	/* sport0 receive control register */
	R0 = 0x013C0971;		/* slave mode, slen = 24, sden_A & schen_A & sden_B & schen_B enabled */
	dm(SRCTL0) = R0;		/* sport 0 receive control register */

	/* sport0 transmit control register */
	R0 = 0x017C8971;		/* slave mode, slen = 24, sden_A & schen_A & sden_B & schen_B enabled */
	dm(STCTL0) = R0;		/* sport 0 transmit control register */
	
	/* sport0 I2S word select (transmit frame sync) divide register */
	R0 = 0x00000000;		/* TCLKDIV=[2xfCLKIN(60MHz)/SCLKfreq(12MHz)]-1 */
	dm(TDIV0) = R0;			/* TFSDIV=[TCLKfrq(12 MHz)/TFSfrq(96.0K)]-1 */

	/* sport0 I2S receive word select divide register */
	R0 = 0x00000000;
	dm(RDIV0) = R0;

	/* sport0 receive and transmit multichannel word enable registers */
	R0 = 0x00000000;  		/* multichannel mode disabled */
	dm(MRCS0) = R0;			
	dm(MTCS0) = R0;			

	/* sport0 transmit and receive multichannel companding enable registers */
	R0 = 0x00000000;		/* no companding */
	dm(MRCCS0) = R0;		/* no companding on receive */
	dm(MTCCS0) = R0;		/* no companding on transmit */

	RTS;

/*----------------------------------------------------------------------------------*/
/* 		DMA Controller Programming For SPORT0 I2S Tx and Rx 		    			*/
/* 										    										*/
/* 		Setup SPORT0 I2S for DMA Chaining:				    						*/
/*----------------------------------------------------------------------------------*/

Program_DMA_Controller_SPT0:
	r1 = 0x0001FFFF;				/* cpx register mask */

	/* sport0 dma channel a control tx chain pointer register */
	r0 = tx0a_buf;
	dm(xmit0a_tcb + 7) = r0;      	/* internal dma address used for chaining*/
	r0 = 1;
	dm(xmit0a_tcb + 6) = r0;      	/* DMA internal memory DMA modifier */
	r0 = 2;
	dm(xmit0a_tcb + 5) = r0;      	/* DMA internal memory buffer count */
	r0 = xmit0a_tcb + 7;			/* get DMA chaining internal mem pointer containing tx_buf address */
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(xmit0a_tcb + 4) = r0;      	/* write DMA transmit block chain pointer to TCB buffer */
	dm(CPT0A) = r0;                 /* transmit block chain pointer, initiate tx0 DMA transfers */

	/* sport0 dma channel b control tx chain pointer register */
	r0 = tx0b_buf;
	dm(xmit0b_tcb + 7) = r0;      	/* internal dma address used for chaining*/
	r0 = 1;
	dm(xmit0b_tcb + 6) = r0;      	/* DMA internal memory DMA modifier */
	r0 = 2;
	dm(xmit0b_tcb + 5) = r0;      	/* DMA internal memory buffer count */
	r0 = xmit0b_tcb + 7;			/* get DMA chaining internal mem pointer containing tx_buf address */
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(xmit0b_tcb + 4) = r0;      	/* write DMA transmit block chain pointer to TCB buffer */
	dm(CPT0B) = r0;                 /* transmit block chain pointer, initiate tx0 DMA transfers */

	/* sport0 dma channel a control rx chain pointer register */
	r0 = rx0a_buf;
	dm(rcv0a_tcb + 7) = r0;       	/* internal dma address used for chaining */
	r0 = 1;
	dm(rcv0a_tcb + 6) = r0;       	/* DMA internal memory DMA modifier */
	r0 = 2;
	dm(rcv0a_tcb + 5) = r0;       	/* DMA internal memory buffer count */
	r0 = rcv0a_tcb + 7;
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(rcv0a_tcb + 4) = r0;       	/* write DMA receive block chain pointer to TCB buffer*/
	dm(CPR0A) = r0;                 /* receive block chain pointer, initiate rx0 DMA transfers */

	/* sport0 dma channel b control rx chain pointer register */
	r0 = rx0b_buf;
	dm(rcv0b_tcb + 7) = r0;       	/* internal dma address used for chaining */
	r0 = 1;
	dm(rcv0b_tcb + 6) = r0;       	/* DMA internal memory DMA modifier */
	r0 = 2;
	dm(rcv0b_tcb + 5) = r0;       	/* DMA internal memory buffer count */
	r0 = rcv0b_tcb + 7;
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(rcv0b_tcb + 4) = r0;       	/* write DMA receive block chain pointer to TCB buffer*/
	dm(CPR0B) = r0;                 /* receive block chain pointer, initiate rx0 DMA transfers */
	
	RTS;

.endseg;