sdram_init.asm

电子元件资料-170M-pdf版.zip

/************************************************************************************

		ADSP-21065L Spinner Board
	   	- SDRAM Interface Initialization
	  	- Programmable I/O Flag  Test

		JT
		ADI DSP Applications Group
		1/28/99
************************************************************************************/
#include "def21065L.h"
#include "new65Ldefs.h"

#define sdram_size 0x3fffff

.SEGMENT/DM segsdram;

.ENDSEG;

.SEGMENT/PM pm_code;

.GLOBAL 	Init_65L_SDRAM_Controller;
.GLOBAL 	Blink_LEDs_Test;

/*************************************************************************************
	Setup '65L Spinner Board SDRAM
	Assumes Micron SDRAM part# MT48LC4M16A2TG-10 on Bittware Spinner Board
		SDCLK=60MHz
		tCK=15ns min @ CL=2	-> SDCL=2
		tRAS=60ns min		-> SDTRAS=4
		tRP=30ns min		-> SDTRP=2
		tREF=64ms/4K rows	-> SDRDIV=(2(30MHz)-CL-tRP-4)64ms/4096=937cycles
	                            
	4 Banks -> SDBN=1
	2 SDRAMs by 16 bits wide total = 4 Meg x 32 Words
	Mapped to MS0 addresses 0x00020000-0x003F7FFF
***************************************************************************************/

Init_65L_SDRAM_Controller:
		ustat1=dm(WAIT);
		bit clr ustat1 0x0000001F;	/*clear MS0 waitstate and mode*/
		dm(WAIT)=ustat1;

		ustat1=937; 				/*refresh rate*/
		dm(SDRDIV)=ustat1;

		ustat1=dm(IOCTL);			/*mask in SDRAM settings*/
		bit set ustat1 SDPSS|SDBN4|SDBS0|SDTRP2|SDTRAS4|SDCL2|SDPGS256;
		dm(IOCTL)=ustat1;
		rts;

/*-------------------------------------------------------------------------------------*/

Blink_LEDs_Test:
		/* Setup FLAG outputs */
		ustat1=dm(IOCTL);
		bit set ustat1 FLG4O|FLG5O|FLG6O|FLG7O|FLG8O|FLG9O;
		dm(IOCTL)=ustat1;			/*flag 5-9 are output*/
		ustat1=0x3f;				/*clear flags to start*/
		dm(IOSTAT)=ustat1;

		/* Blink flags 5 times */
		lcntr=10, do blink_loop until lce;
			lcntr=15000000;
			do delay until lce;
delay:			nop;

			ustat1=dm(IOSTAT);
			bit tgl ustat1 FLG4|FLG5|FLG6|FLG7|FLG8|FLG9;
blink_loop:	dm(IOSTAT)=ustat1;
		rts;

.ENDSEG;