ad1819_sport1tx_isr.asm

电子元件资料-170M-pdf版.zip

/* **************************************************************************************************
/                                                                                                   /
/                            AD1819A - SPORT1 TX INTERRUPT SERVICE ROUTINE                          /
/                                                                                                   /
/    Receives MIC1/Line input data from the AD1819A via SPORT1 and transmits processed audio data   /
/    back out to the AD1819A Stereo DACs/Line Outputs                                               /
/                                                                                                   /
/    This SPORT1 tx ISR version uses the ADC Valid Bits to send and recieve audio samples at        /
/    different rates other than the default 48 kHz.  Assuming the L/R ADCs and DACs are running     /
/    at the same sample rate, we transmit a processed sample for every newly recieved ADC sample.   /
/                                                                                                   /
*****************************************************************************************************
                                                                                                    /
  This Serial Port 1 Transmit Interrupt Service Routine performs arithmetic computations on         /
  the SPORT1 receive DMA buffer (rx_buf) and places results to SPORT1 transmit DMA buffer (tx_buf)  /
                                                                                                    /
 rx1a_buf[5] - DSP SPORT recieve buffer                                                             /
 Slot # Description                             DSP Data Memory Address                             /
 ------ --------------------------------------  -------------------------------------------------   /
 0      AD1819A Tag Phase                       DM(rx1a_buf + 0) = DM(rx1a_buf + TAG_PHASE)         /
 1      Status Address Port                     DM(rx1a_buf + 1) = DM(rx1a_buf + STATUS_ADDRESS_SLOT)/
 2      Status Data Port                        DM(rx1a_buf + 2) = DM(rx1a_buf + STATUS_DATA_SLOT)  /
 3      Master PCM Capture (Record) Left Chan.  DM(rx1a_buf + 3) = DM(rx1a_buf + LEFT)              /
 4      Master PCM Capture Right Channel        DM(rx1a_buf + 4) = DM(rx1a_buf + RIGHT)             /
                                                                                                    /
 tx1a_buf[7] - DSP SPORT transmit buffer                                                            /
 Slot # Description                             DSP Data Memory Address                             /
 ------ --------------------------------------  --------------------------------------------------  /
 0      ADSP-21065L Tag Phase                   DM(tx1a_buf + 0) = DM(tx1a_buf + TAG_PHASE)         /
 1      Command Address Port                    DM(tx1a_buf + 1) = DM(tx1a_buf + COMMAND_ADDRESS_SLOT)/
 2      Command Data Port                       DM(tx1a_buf + 2) = DM(tx1a_buf + COMMAND_DATA_SLOT) /
 3      Master PCM Playback Left Channel        DM(tx1a_buf + 3) = DM(tx1a_buf + LEFT)              /
 4      Master PCM Playback Right Channel       DM(tx1a_buf + 4) = DM(tx1a_buf + RIGHT)             /
 5      Dummy Slot (Not Used)                                                                       /
 6      Dummy Slot (Not used)                                                                       /
                                                                                                    /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~/
                                                                                                    /
   ** IMPORTANT SPORT-AD1819A CODEC TDM TIMING NOTES:                                               /
   -------------------------------------------------                                                /
   For SPORT TX and RX DMA chaining in TDM mode with equivalent DMA buffer sizes & active TDM       /
   channels, the DMA interrupts are alway at least two timeslots apart.  That is because the tx     /
   TCB initially places the first two words from the tx DMA buffer into the SPORT1 TX buffer        /
   registers.  This automatically decrements the tx DMA count by two.                               /
                                                                                                    /
   For an active 5-channel TX and RX DMA/TDM scheme with SPORT TX ISR processing: after the         /
   assertion of the TX DMA interrupt, we would need to wait until the RX DMA brings in data for     /
   channels 4 and 5 for the current frame in which the rx ADC valid bits and DAC request bits are   /
   set.                                                                                             /
                                                                                                    /
   So, before timeslot 0 rx and tx, the rx DMA count = 5, while the tx DMA count = 3.  The          /
   transmit interrupt occurs when the tx count = 0. This occurs immediately after timeslot 2. While /
   this occurs, the tx data for the left channel is shifting out of this Tx-shift register in       /
   slot 3, while the right tx data for channel 4 is in the TX1A register queue.                     /
                                                                                                    /
   After both the transmit and recieve interrupts are latched in the current frame (after           /
   timeslot 5), the TCBs will be reloaded, but no DMA internal memory transfers will occur until    /
   the next frame sync, which would occur 11 time-slots later. After each reloading of the tx       /
   TCB, the first 2 words of the TX DMA buffer are automatically loaded into the TX queue as the    /
   previous 2 words at the end of the last TX DMA transfer are shifted out of the SPORT tx shift    /
   register.                                                                                        /
                                                                                                    /
             __                                                                          __         /
   RFS1  ___|  |________________________________________________________________________|  |_       /
                                                                                                    /
   DR1_A        < SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT5 > ----------//--------------            /
                                                              No activity on Slots 5 - 15           /
                                                                                                    /
   CR1A         5        4        3        2        1        0 <-- RX Interrupt Here                /
   (DMA RX Count Reg)                                                                               /
                                                                                                    /
                                                                                                    /
   DT1_A        < SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT5 > ----------//----------------          /
                                                              No activity on Slots 5 - 15           /
                                                                                                    /
   CT1A         3        2        1        0 <-- TX Interrupt Here                                  /
   (DMA TX Count Reg)                            TX queue reloaded with 1st two tx_buf values       /
                                                                                                    /
            (1 / 12.288 MHz SCLK) x (16-bits/timeslot) x (2 timeslots) = 2.604 microseconds         /
             1 / 60 MHz Instruction Execution = 16.667 nanoseconds per instruction                  /
             2.604 microseconds / 16.667 nanoseconds = 156.25 = 157 DSP cycles                      /
                                                                                                    /
                                                                                                    /
   Keeping these differences in interrupt timing between the transmit and recieve channels, we can  /
   implement different methods to ensure proper data and tag alignment for processing data at       /
   sample rates < 48 kHz with a 48 kHz audio frame rate.                                            /
                                                                                                    /
        ** Extend the TX DMA buffer size to 7 in length and enable 7 tx TDM channels, as is done    /
        in this code example.  This guarantees that by the time we generate a TX DMA interrupt,     /
        the RX left and right data for the current frame have been recieved in time before we       /
        read the samples. Slots 5 and 6 are dummy slots and never used.  However, the DSP core      /
        is not held up waiting for the current rx left and right channels to be DMA'ed into RX_BUF. /
        In order to implement this with the 21065L EZ-LAB RS232 Debugger, the user is required to   /
        run a SPORT1 register clear routine to reset SPORT1 MCM and DMA activity.                   /
                                                                                                    /
   Using this method,  we have approximately 75 DSP cycles upon entering the TX interrupt           /
   service routine to write to the DM(TX_BUF + 0), which is the TX TAG phase slot, in order         /
   that our left and right transmit data slots go out within the same audio frame as the TAG        /
   slot.  If not done in time, we would send data out in the current frame, but the tag bits would  /
   get sent in the following frame.  We would then risk the dropping of processed samples, and      /
   severe audible distortion results. The example below ensures that the tx TAG bits are set at     /
   the beginning of the ISR before any audio processing is done.                                    /
                                                                                                    /
                                                                                                    /
   JT                                                                                               /
   ADI DSP Applications                                                                             /
   Rev 2.0                                                                                          /
   4/29/99                                                                                          /
                                                                                                    /
****************************************************************************************************/

/* ADSP-21060 System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"

/* AD1819 TDM Timeslot Definitions */
#define		TAG_PHASE				0
#define		COMMAND_ADDRESS_SLOT	1
#define		COMMAND_DATA_SLOT		2
#define		STATUS_ADDRESS_SLOT		1
#define		STATUS_DATA_SLOT		2
#define		LEFT					3
#define		RIGHT					4

/* Left and Right ADC valid Bits used for testing of valid audio data in current TDM frame */
#define		M_Left_ADC				12
#define		M_Right_ADC				11
#define		DAC_Req_Left			0x80
#define		DAC_Req_Right			0x40

.GLOBAL		Process_AD1819_Audio_Samples;
.GLOBAL 	Left_Channel_In;
.GLOBAL 	Right_Channel_In;
.GLOBAL 	Left_Channel_Out;
.GLOBAL 	Right_Channel_Out;
.GLOBAL 	Left_Channel;
.GLOBAL 	Right_Channel;
.GLOBAL		RX_left_flag, RX_right_flag;
.EXTERN		tx1a_buf;
.EXTERN		rx1a_buf;
.EXTERN		Slapback_Echo;
.EXTERN		Stereo_Double_Tracking;
.EXTERN		effects_counter;