def21065l.h

电子元件资料-170M-pdf版.zip

/* -----------------------------------------------------------------------------
def21065L.h - SYSTEM AND IOP REGISTER BIT AND ADDRESS DEFINITIONS FOR ADSP-21065L
	
Last Modification on: Feb-15-95

This include file contains a list of macro defines to enable the programmer to
use symbolic names for all of the system register bits for the ADSP-21065L.
It also contains macros for the IOP register addresses and some bit fields.
-------------------------------------------------------------------------------*/	
/* MODE1 register */
#define BR8     0x00000001 /* Bit  0: Bit-reverse for I8                      */
#define BR0     0x00000002 /* Bit  1: Bit-reverse for I0 (uses DMS0- only )   */
#define SRCU    0x00000004 /* Bit  2: Alt. register select for comp. units    */
#define SRD1H   0x00000008 /* Bit  3: DAG1 alt. register select (7-4)         */
#define SRD1L   0x00000010 /* Bit  4: DAG1 alt. register select (3-0)         */
#define SRD2H   0x00000020 /* Bit  5: DAG2 alt. register select (15-12)       */
#define SRD2L   0x00000040 /* Bit  6: DAG2 alt. register select (11-8)        */
#define SRRFH   0x00000080 /* Bit  7: Register file alt. select for R(15-8)   */
#define SRRFL   0x00000400 /* Bit 10: Register file alt. select for R(7-0)    */
#define NESTM   0x00000800 /* Bit 11: Interrupt nesting enable                */
#define IRPTEN  0x00001000 /* Bit 12: Global interrupt enable                 */
#define ALUSAT  0x00002000 /* Bit 13: Enable ALU fixed-pt. saturation         */
#define SSE     0x00004000 /* Bit 14: Enable short word sign extension        */
#define TRUNC   0x00008000 /* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest  */
#define RND32   0x00010000 /* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd  */
#define CSEL	0x00060000 /* Bit 17-18: CSelect: Bus Mastership	      */

/* MODE2 register */
#define IRQ0E   	0x00000001 /* Bit  0: IRQ0- 1=edge sens. 0=level sens.        */
#define IRQ1E   	0x00000002 /* Bit  1: IRQ1- 1=edge sens. 0=level sens.        */
#define IRQ2E   	0x00000004 /* Bit  2: IRQ2- 1=edge sens. 0=level sens.        */
#define PERIOD_CNT0	0x00000008 /* Bit  3: Enable Period Count                     */
#define CADIS   	0x00000010 /* Bit  4: Cache disable                           */
#define TIMEN0   	0x00000020 /* Bit  5: Timer0 enable                           */
#define BUSLK   	0x00000040 /* Bit  6: External bus lock                       */
#define PWMOUT0		0x00000080 /* Bit  7: PWMOUT/WIDTH_CNT control-Timer0         */
#define INT_HI0		0x00000100 /* Bit  8: Interrupt Vector location               */
#define PULSE_HI0	0x00000200 /* Bit  9: Pulse transition edge select            */
#define PERIOD_CNT1     0x00000400 /* Bit 10: Enable Period Count                     */
#define TIMEN1   	0x00000800 /* Bit 11: Timer0 enable                           */
#define PWMOUT1   	0x00001000 /* Bit 12: PWMOUT/WIDTH_CNT control-Timer1         */
#define INT_HI1   	0x00002000 /* Bit 13: Interrupt Vector location               */
#define PULSE_HI1	0x00004000 /* Bit 14: Pulse transition edge select            */
#define FLG0O   	0x00008000 /* Bit 15: FLAG0 1=output 0=input                  */                 
#define FLG1O   	0x00010000 /* Bit 16: FLAG1 1=output 0=input                  */
#define FLG2O   	0x00020000 /* Bit 17: FLAG2 1=output 0=input                  */
#define FLG3O   	0x00040000 /* Bit 18: FLAG3 1=output 0=input                  */
#define CAFRZ   	0x00080000 /* Bit 19: Cache freeze                            */

/* ASTAT register */
#define AZ      0x00000001 /* Bit  0: ALU result zero or fltg-pt. underflow   */
#define AV      0x00000002 /* Bit  1: ALU overflow                            */
#define AN      0x00000004 /* Bit  2: ALU result negative                     */
#define AC      0x00000008 /* Bit  3: ALU fixed-pt. carry                     */
#define AS      0x00000010 /* Bit  4: ALU X input sign (ABS and MANT ops)     */
#define AI      0x00000020 /* Bit  5: ALU fltg-pt. invalid operation          */
#define MN      0x00000040 /* Bit  6: Multiplier result negative              */
#define MV      0x00000080 /* Bit  7: Multiplier overflow                     */
#define MU      0x00000100 /* Bit  8: Multiplier fltg-pt. underflow           */
#define MI      0x00000200 /* Bit  9: Multiplier fltg-pt. invalid operation   */
#define AF      0x00000400 /* Bit 10: ALU fltg-pt. operation                  */
#define SV      0x00000800 /* Bit 11: Shifter overflow                        */
#define SZ      0x00001000 /* Bit 12: Shifter result zero                     */
#define SS      0x00002000 /* Bit 13: Shifter input sign                      */
#define BTF     0x00040000 /* Bit 18: Bit test flag for system registers      */
#define FLG0    0x00080000 /* Bit 19: FLAG0 value                             */
#define FLG1    0x00100000 /* Bit 20: FLAG1 value                             */
#define FLG2    0x00200000 /* Bit 21: FLAG2 value                             */
#define FLG3    0x00400000 /* Bit 22: FLAG3 value                             */
#define CACC0   0x01000000 /* Bit 24: Compare Accumulation Bit 0              */
#define CACC1   0x02000000 /* Bit 25: Compare Accumulation Bit 1              */
#define CACC2   0x04000000 /* Bit 26: Compare Accumulation Bit 2              */
#define CACC3   0x08000000 /* Bit 27: Compare Accumulation Bit 3              */
#define CACC4   0x10000000 /* Bit 28: Compare Accumulation Bit 4              */
#define CACC5   0x20000000 /* Bit 29: Compare Accumulation Bit 5              */
#define CACC6   0x40000000 /* Bit 30: Compare Accumulation Bit 6              */
#define CACC7   0x80000000 /* Bit 31: Compare Accumulation Bit 7              */

/* STKY register */
#define AUS     0x00000001 /* Bit  0: ALU fltg-pt. underflow                  */
#define AVS     0x00000002 /* Bit  1: ALU fltg-pt. overflow                   */
#define AOS     0x00000004 /* Bit  2: ALU fixed-pt. overflow                  */ 
#define AIS     0x00000020 /* Bit  5: ALU fltg-pt. invalid operation          */
#define MOS     0x00000040 /* Bit  6: Multiplier fixed-pt. overflow           */
#define MVS     0x00000080 /* Bit  7: Multiplier fltg-pt. overflow            */
#define MUS     0x00000100 /* Bit  8: Multiplier fltg-pt. underflow           */
#define MIS     0x00000200 /* Bit  9: Multiplier fltg-pt. invalid operation   */
#define CB7S    0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow         */
#define CB15S   0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow        */
#define PCFL    0x00200000 /* Bit 21: PC stack full                           */
#define PCEM    0x00400000 /* Bit 22: PC stack empty                          */
#define SSOV    0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT) */
#define SSEM    0x01000000 /* Bit 24: Status stack empty                      */
#define LSOV    0x02000000 /* Bit 25: Loop stack overflow                     */
#define LSEM    0x04000000 /* Bit 26: Loop stack empty                        */

/* IRPTL and IMASK and IMASKP registers */
#define RSTI    0x00000002 /* Bit  1: Offset: 04: Reset                       */
#define SOVFI   0x00000008 /* Bit  3: Offset: 0c: Stack overflow              */
#define TMZHI   0x00000010 /* Bit  4: Offset: 10: Timer = 0 (high priority)   */
#define VIRPTI  0x00000020 /* Bit  5: Offset: 14: Vector interrupt            */
#define IRQ2I   0x00000040 /* Bit  6: Offset: 18: IRQ2- asserted              */
#define IRQ1I   0x00000080 /* Bit  7: Offset: 1c: IRQ1- asserted              */
#define IRQ0I   0x00000100 /* Bit  8: Offset: 20: IRQ0- asserted              */
#define SPR0I	0x00000400 /* Bit 10: Offset: 28: SPORT0 receive 	      */
#define SPR1I	0x00000800 /* Bit 11: Offset: 2c: SPORT1 receive    	      */
#define SPT0I	0x00001000 /* Bit 12: Offset: 30: SPORT0 transmit  	      */
#define SPT1I	0x00002000 /* Bit 13: Offset: 34: SPORT1 transmit  	      */
#define EP0I	0x00010000 /* Bit 16: Offset: 40: External port channel 0 DMA */
#define EP1I	0x00020000 /* Bit 17: Offset: 44: External port channel 1 DMA */
#define CB7I    0x00200000 /* Bit 21: Offset: 54: Circ. buffer 7 overflow     */
#define CB15I   0x00400000 /* Bit 22: Offset: 58: Circ. buffer 15 overflow    */
#define TMZLI   0x00800000 /* Bit 23: Offset: 5c: Timer = 0 (low priority)    */
#define FIXI    0x01000000 /* Bit 24: Offset: 60: Fixed-pt. overflow          */
#define FLTOI   0x02000000 /* Bit 25: Offset: 64: fltg-pt. overflow           */
#define FLTUI   0x04000000 /* Bit 26: Offset: 68: fltg-pt. underflow          */
#define FLTII   0x08000000 /* Bit 27: Offset: 6c: fltg-pt. invalid            */
#define SFT0I   0x10000000 /* Bit 28: Offset: 70: user software int 0         */
#define SFT1I   0x20000000 /* Bit 29: Offset: 74: user software int 1         */
#define SFT2I   0x40000000 /* Bit 30: Offset: 78: user software int 2         */
#define SFT3I   0x80000000 /* Bit 31: Offset: 7c: user software int 3         */

/* SYSCON Register */
#define SYSCON 0x00	   /* Memory mapped System Configuration Register     */
#define SRST   0x00000001  /* Soft Reset				      */
#define BSO    0x00000002  /* Boot Select Override			      */
#define IIVT   0x00000004  /* Internal Interrupt Vector Table		      */
#define HBW00  0x00000000  /* Host Bus Width: 32bit			      */
#define HBW01  0x00000010  /* Host Bus Width: 16bit			      */
#define HBW10  0x00000020  /* Host Bus Width: 8bit			      */
#define HMSWF  0x00000040  /* Host packing order (0 = LSW first, 1 = MSW)     */
#define HPFLSH 0x00000080  /* Host pack flush				      */
#define IMDW0X 0x00000100  /* Internal memory block 0, extended data (40 bit) */
#define IMDW1X 0x00000200  /* Internal memory block 1, extended data (40 bit) */
#define EBPR00 0x00000000  /* External bus priority: Even		      */
#define EBPR01 0x00010000  /* External bus priority: Core has priority	      */
#define EBPR10 0x00020000  /* External bus priority: IO has priority	      */
#define DCPR   0x00040000  /* Select rotating access priority on DMA6 - DMA9  */

/* SYSTAT Register */
#define SYSTAT 0x03	   /* Memory mapped System Status Register	      */
#define HSTM   0x00000001  /* Host is the Bus Master			      */
#define BSYN   0x00000002  /* Bus arbitration logic is synchronized	      */
#define CRBM   0x00000030  /* Current ADSP21065L Bus Master		      */
#define IDC    0x00000300  /* ADSP21065L ID Code			      */
#define VIPD   0x00002000  /* Vector interrupt pending (1 = pending)	      */
#define HPS    0x00004000  /* Host pack status				      */

/*------------------------  SYSTEM registers  -------------------------------------*/

#define		SYSCON		0x00
#define		VIRPT		0x01
#define		WAIT		0x02
#define		SYSTAT		0x03

/*-------------------------  DMA BUFFER registers --------------------------*/

/* These are old register names  */

#define		DMAB0		0x04
#define		DMAB1		0x05

/* These are the new register names  */

#define		EPB0		0x04
#define		EPB1		0x05

/*-------------------------  MESSAGE registers  ----------------------------*/

#define		MSGR_0		0x08
#define		MSGR_1		0x09
#define		MSGR_2		0x0a
#define		MSGR_3		0x0b
#define		MSGR_4		0x0c
#define		MSGR_5		0x0d
#define		MSGR_6		0x0e
#define		MSGR_7		0x0f

/*---------------------  MISCELLANEOUS registers  ------------------------*/

#define		BMAX		0x18
#define		BCNT		0x19
#define		ELAST		0x1b

/*---------------------  DMAC registers  ---------------------------------*/

/* These are the old register names  */

#define		DMAC6		0x1c
#define		DMAC7		0x1d

/* These are the new register names  */

#define		DMAC0		0x1c
#define		DMAC1		0x1d

/*--------------------------- 21065L registers  --------------------------*/

#define         SDRDIV          0x20
#define         SDRCNT          0x21
#define         SDADDLAT        0x22

#define         TPERIOD0        0x28
#define         TPWIDTH0        0x29
#define         TCOUNT0         0x2a
#define         TPERIOD1        0x2b
#define         TPWIDTH1        0x2c
#define         TCOUNT1         0x2d
#define         IOCTL           0x2e
#define         IOSTAT          0x2f

/*---------------------  DMA ADDRESS registers ---------------------------*/

#define		II0		0x60
#define		IM0		0x61
#define		C0		0x62
#define		CP0		0x63
#define		GP0		0x64
#define		DB0		0x65
#define		DA0		0x66

#define		II1		0x68
#define		IM1		0x69
#define		C1		0x6A
#define		CP1		0x6B
#define		GP1		0x6C
#define		DB1		0x6D
#define		DA1		0x6E