ad1819a_initialization.asm

电子元件资料-170M-pdf版.zip

/***   AD1819a_initialization.ASM   *********************************************
*                                                                               *
*       AD1819/ADSP-21065L SPORT1 Initialization Driver                         *
*       Developed using the ADSP-21065L EZ-LAB Evaluation Platform              *
*                                                                               *
*       This version sets up codec communication for Variable Sample Rate       *
*       Support.  After codec register programming, the ADCs and DACs are       *
*       powered down and back up again, so left/right valid bits and DAC        *
*       requests occur simultaneously in the same audio frame.                  *
*                                                                               *
*       For efficient handling of Tag bits/ADC valid/DAC requests, the codec	*
*       ISR is processes using the SPORT1 TX (vs RX) interrupt. The SPORT1 TX   *
*       interrupt is used to first program the AD1819A registers, with only     *
*       an RTI at that vector location. After codec initialization, the SPORT1  *
*       TX ISR jump label is installed, replacing an 'RTI' instruction, so that *
*       normal codec audio processing begins at that point.                     *
*                                                                               *
*                                                   John Tomarakos              *
*                                                   ADI DSP Applications Group	*
*                                                   Revision 3.0                *
*                                                   04/29/99                    *
*                                                                               *
*********************************************************************************/
	
/* ADSP-21060 System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"
			   
.EXTERN		spt1_svc;
.GLOBAL		Program_SPORT1_Registers;
.GLOBAL		Program_DMA_Controller_SPT1;
.GLOBAL		AD1819_Codec_Initialization;
.GLOBAL		tx1a_buf;
.GLOBAL		rx1a_buf;
.EXTERN		Clear_All_SPT1_Regs;

/* AD1819 Codec Register Address Definitions */
#define		REGS_RESET				0x0000
#define		MASTER_VOLUME			0x0200
#define		RESERVED_REG_1			0x0400
#define		MASTER_VOLUME_MONO		0x0600	
#define		RESERVED_REG_2			0x0800
#define		PC_BEEP_Volume			0x0A00
#define		PHONE_Volume			0x0C00
#define		MIC_Volume				0x0E00
#define		LINE_IN_Volume			0x1000
#define		CD_Volume				0x1200
#define		VIDEO_Volume			0x1400
#define		AUX_Volume				0x1600
#define		PCM_OUT_Volume			0x1800
#define		RECORD_SELECT			0x1A00
#define		RECORD_GAIN				0x1C00
#define		RESERVED_REG_3			0x1E00
#define		GENERAL_PURPOSE			0x2000
#define		THREE_D_CONTROL_REG		0x2200
#define		RESERVED_REG_4			0x2400
#define		POWERDOWN_CTRL_STAT		0x2600
#define		SERIAL_CONFIGURATION	0x7400
#define		MISC_CONTROL_BITS		0x7600
#define		SAMPLE_RATE_GENERATE_0	0x7800
#define		SAMPLE_RATE_GENERATE_1	0x7A00
#define		VENDOR_ID_1				0x7C00
#define		VENDOR_ID_2				0x7E00

/* Mask bit selections in Serial Configuration Register for 
   accessing registers on any of the 3 codecs */
#define		MASTER_Reg_Mask			0x1000
#define		SLAVE1_Reg_Mask			0x2000
#define		SLAVE2_Reg_Mask			0x4000
#define		MASTER_SLAVE1			0x3000
#define		MASTER_SLAVE2			0x5000
#define		MASTER_SLAVE1_SLAVE2	0x7000

/* Macros for setting Bits 15, 14 and 13 in Slot 0 Tag Phase */
#define		ENABLE_VFbit_SLOT1_SLOT2	0xE000
#define		ENABLE_VFbit_SLOT1			0xC000

/* AD1819 TDM Timeslot Definitions */
#define		TAG_PHASE				0
#define		COMMAND_ADDRESS_SLOT	1
#define		COMMAND_DATA_SLOT		2
#define		STATUS_ADDRESS_SLOT		1
#define		STATUS_DATA_SLOT		2
#define		LEFT					3
#define		RIGHT					4

#define     AD1819_RESET_CYCLES 	60
			/* ad1819 RESETb spec = 1.0(uS) min */
			/* 60(MIPs) = 16.67 (nS) cycle time, therefore >=    40 cycles */
#define     AD1819_WARMUP_CYCLES    60000
			/* ad1819 warm-up = 1.0(mS) */
			/* 60(MIPs) = 16.67 (nS) cycle time, therefore >= 40000 cycles */


/*---------------------------------------------------------------------------*/
.segment /dm    dm_codec;
.var rx1a_buf[5]; 	/* receive buffer */

					/* transmit buffer */ 
.var tx1a_buf[7] = ENABLE_VFbit_SLOT1_SLOT2, 	/* set valid bits for slot 0, 1, and 2 */
		 SERIAL_CONFIGURATION, 			/* serial configuration register address */
		 0xFF80, 						/* initially set to 16-bit slot mode for ADI SPORT compatibility*/
		 0x0000, 						/* stuff other slots with zeros for now */
		 0x0000,
		 0x0000,
		 0x0000; 		
		 /* slots 5 and 6 are dummy slots, to allow enough time in the TX ISR to go     */
		 /* get rx slots 4 & 5 data in same audio frame as the ADC valid tag bits.      */
		 /* This is critical for slower sample rates, where you may not have valid data */
		 /* every rx audio frame. So you want to make sure there is valid right         */
		 /* channel data in the same rx DMA buffer fill as the detection of an ADC      */
		 /* valid right bit.  These extra slots are required ONLY for fs < 48 kHz.	    */
						
.var rcv_tcb[8]  = 0, 0, 0, 0, 0, 5, 1, 0;      /* receive tcb */
.var xmit_tcb[8] = 0, 0, 0, 0, 0, 7, 1, 0;      /* transmit tcb */

/* Codec register initializations */
/* Refer to AD1819 Data Sheet for register bit assignments */
#define	Select_LINE_INPUTS	0x0404	/* LINE IN - 0X0404, Mic In - 0x0000 */
#define Select_MIC_INPUT	0x0000
#define Line_Level_Volume	0x0000	/* 0 dB for line inputs */
#define Mic_Level_Volume	0x0F0F
#define	Sample_Rate			23456
#define	Sample_Rate_48kHz	48000

.var Init_Codec_Registers[34] =
	MASTER_VOLUME,			0x0000,				/* Master Volume set for no attenuation */
	MASTER_VOLUME_MONO,		0x8000,				/* Master Mono volume is muted */
	PC_BEEP_Volume,			0x8000,				/* PC volume is muted */
	PHONE_Volume,			0x8008,				/* Phone Volume is muted */
	MIC_Volume,				0x8008,				/* MIC Input analog loopback is muted */
	LINE_IN_Volume,			0x8808,				/* Line Input analog loopback is muted */
	CD_Volume,				0x8808,				/* CD Volume is muted */
	VIDEO_Volume,			0x8808,				/* Video Volume is muted */
	AUX_Volume,				0x8808,	 			/* AUX Volume is muted */
	PCM_OUT_Volume,			0x0808,				/* PCM out from DACs is 0 db gain for both channels */
	RECORD_SELECT,			Select_MIC_INPUT,   /* Record Select on Line Inputs for L/R channels */
	RECORD_GAIN,			Mic_Level_Volume, 	/* Record Gain set for 0 dB on both L/R channels */
	GENERAL_PURPOSE,		0x0000,				/* 0x8000, goes through 3D circuitry */
	THREE_D_CONTROL_REG,	0x0000,				/* no phat stereo */
	MISC_CONTROL_BITS,		0x0000,				/* use SR0 for both Left and Right ADCs and DACs, repeat sample */
	SAMPLE_RATE_GENERATE_0,	Sample_Rate_48kHz,	/* user selectable sample rate */
	SAMPLE_RATE_GENERATE_1,	48000;				/* Sample Rate Generator 1 not used in this example */

.var Codec_Init_Results[34] = 	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,		
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0,	
	0,		0;

.endseg;

.SEGMENT /pm 	pm_code;
	
/* ---------------------------------------------------------------------------------------------*/
/* Sport1 Control Register Programming 							  	                            */
/* Multichannel Mode dma w/ chain, erly fs, act hi fs, fall edge, no pack, data=16/big/zero 	*/
/* ---------------------------------------------------------------------------------------------*/

Program_SPORT1_Registers:
	/* This is required for disabling SPORT config for EZLAB RS232 debugger */
	CALL Clear_All_SPT1_Regs;	/* Clear and Reset SPORT1 and DMAs */
								
	/* sport1 receive control register */
	R0 = 0x0F8C40F0;			/* 16 chans, int rfs, ext rclk, slen = 15, sden & schen enabled */
	dm(SRCTL1) = R0;			/* sport 0 receive control register */