sport0_i2s_rx_isr.asm

电子元件资料-170M-pdf版.zip

/* **************************************************************************************************
*                                                                                                   *
*				              SPORT0 I2S RX INTERRUPT SERVICE ROUTINE                               *
*                                                                                                   *
*   Receives loopback data from SPORT0 I2S TX pins via SPORT0 I2S RX and then sends the audio data  *
*   back out to the AD1819A Stereo DACs/Line Outputs                                                *
*                                                                                                   *
*                                                                                                   *			
*---------------------------------------------------------------------------------------------------* 
*                                                                                                   *
*   Serial Port 0 Recieve Interrupt Service Routine performs a loopback on SPORT1 AD1819A audio     *
*   dma buffer (rx1a_buf) and sends results to SPORT1 transmit data dma buffer (tx1a_buf)           *	
*                                                                                                   *
*   rx0a_buf[2] - DSP SPORT0 I2S recieve buffer                                                     *
*   channel Description                       DSP Data Memory Address                               *
*   ------  --------------------------------  --------------------------------------------          *
*   0       I2S Left Channel Data             DM(rx0a_buf + 0) = DM(rx0a_buf + LEFT)                *
*   1       I2S Right Channel Data            DM(rx0a_buf + 1) = DM(rx0a_buf + RIGHT)               *
*                                                                                                   *
*   rx0a_buf[2] - DSP SPORT0 I2S transmit buffer                                                    *
*   channel # Description                     DSP Data Memory Address                               *
*   ------  --------------------------------- --------------------------------------------          *
*   0       I2S Left Channel TX Data          DM(tx0a_buf + 0) = DM(tx0a_buf + LEFT)                *
*   1       I2S Right Channel TX Data         DM(tx0a_buf + 1) = DM(tx0a_buf + RIGHT)               *
*                                                                                                   *
*****************************************************************************************************/

/* ADSP-21065L System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"

/* AD1819 SPORT0 Rx and Tx Timeslot Definitions */
#define		LEFT			0
#define		RIGHT			1

.GLOBAL		Process_I2S_Stereo_Data;
.EXTERN 	Left_Channel_In;
.EXTERN 	Right_Channel_In;
.EXTERN		Left_Channel_Out;
.EXTERN		Right_Channel_Out;
.GLOBAL		rx0a_buf;
.GLOBAL		tx0a_buf;
.EXTERN		Slapback_Echo;

.segment /dm    dm_data;

.VAR 		I2S_Left_Channel;
.VAR 		I2S_Right_Channel;
.VAR		I2S_timer = 0x00000000;

.endseg;

.segment /pm pm_code;

Process_I2S_Stereo_Data:
	bit set mode1 SRRFL;				/* enable secondary registers R0-R7 */
	nop;								/* 1 cycle latency writing to Mode1 register */

get_prior_i2s_tx_data:	
	/* get previous SPORT0 loopback'ed i2s left and right data */
	/* we are getting I2S data that was send in our previous SPORT0 interrupt, and then
	   feeding this audio data back to the AD1819a DACs */	
        r0 = dm(rx0a_buf + LEFT);		/* Get i2s left channel rx data */
        r1 = dm(rx0a_buf + RIGHT);		/* Get i2s right channel rx data */

send_audio_to_AD1819a:
	dm(Left_Channel_Out) = r0;			
	dm(Right_Channel_Out) = r1;

	/* transmit new AD1819a ADC data out of SPORT0 i2s port */
tx_ADC_data_out_I2s:
	/* r0 = dm(i1,m1); */ 				/* get sine data */
	/* r1 = dm(i2,m2); */				/* get sine data */
	r0 = dm(Left_Channel_In); 			/* get AD1819a Left ADC channel data */
	r1 = dm(Right_Channel_In); 			/* get AD1819 Right ADC channel data */
	dm(tx0a_buf + LEFT) = r0;			/* send i2s left channel tx data */
	dm(tx0a_buf + RIGHT) = r1;			/* send i2s right channel tx data */

i2s_tx_done:
	r0=dm(I2S_timer);					/* get last I2S ISR count */
	r0=r0+1;							/* increment counter */
	dm(I2S_timer)=r0;					/* save updated I2S ISR count */

	rti(db);							/* return from interrupt, delayed branch */
	bit clr mode1 SRRFL;				/* restore primary registers R0-R7 */
	nop;								/* 1 cycle latency writing to MODE1 register */

/* ----------------------------------------------------------------------------------------- */ 

.endseg;