📄 sport0_i2smode_init.asm
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/* ********************************************************************************************** */
/* SPORT0 I2S Mode Initialization */
/* */
/* These assembly routines set up the ADSP-21065L SPORT0 registers for I2S mode for */
/* transmitting and recieving of data at 48 KHz. This routine will set up DMA chaining on */
/* SPORT0 to recieve data coming from the AD1819a, do an I2S loopback on SPORT0 on the */
/* incoming AD1819a audio data, and the results of the loopback will be sent to the AD1819a */
/* DACs. In addition, DMA chaining is set up for the B channels to to a SPORT0-B tx-rx */
/* loopback of initialized data initialized in the transmit B buffer. These I2S routines */
/* can be used as a programming reference to test the I2S ports 'digital wire' functionality.*/
/* */
/* For this test case, the transmitter is an I2S master, the reciever is an I2S slave */
/* device. */
/* */
/* NOTE: To run this example using the EMAFE interface on the 21065L EZ-LAB board, you must */
/* connect RCLK0(pin C26) to TCLK0(pin A26), RFS0 (pin C27) to TFS0 (A27), DR0A(pin C28) */
/* to DT0A(pin A28) and DR0B(pin B29) to DT0B(pin 30). Refer to EMAFE pin settings in */
/* Chapter 6 of the 21065L EZ-LAB manual. */
/* */
/* By: John Tomarakos */
/* ADI DSP Applications */
/* Rev 1.0, 12/15/98 */
/* Rev 1.1, 1/11/98 */
/* */
/* ********************************************************************************************** */
/* ADSP-21065L System Register bit definitions */
#include "def21065l.h"
#include "new65Ldefs.h"
.GLOBAL Program_DMA_Controller_SPT0;
.GLOBAL Program_I2Smode_SPORT0_Registers;
.GLOBAL rx0a_buf;
.GLOBAL tx0a_buf;
.GLOBAL rx0b_buf;
.GLOBAL tx0b_buf;
.segment /dm dm_I2S;
/* define buffer size to match I2S TDM stereo channels with AD1819A audio channels */
#define STEREO_LR 2
.var rx0a_buf[STEREO_LR]; /* primary a stereo receive buffer */
.var tx0a_buf[STEREO_LR]; /* primary a stereo transmit buffer */
.var rx0b_buf[8]; /* secondary receive b buffer */
.var tx0b_buf[8] = 0x11111111, /* secondary transmit b buffer */
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888;
.var rcv0a_tcb[8] = 0, 0, 0, 0, 0, 2, 1, 0; /* receive a tcb */
.var xmit0a_tcb[8] = 0, 0, 0, 0, 0, 2, 1, 0; /* transmit a tcb */
.var rcv0b_tcb[8] = 0, 0, 0, 0, 0, 8, 1, 0; /* receive b tcb */
.var xmit0b_tcb[8] = 0, 0, 0, 0, 0, 8, 1, 0; /* transmit b tcb */
.endseg;
.segment /pm pm_code;
/* //////////////////////////////////////////////////////////////////////////////////////////// */
/* Sport0 Control Register Programming */
/* I'squared'S Mode dma w/ chain, erly fs, act hi fs, fall edge, no pack, data=16/big/zero */
/* //////////////////////////////////////////////////////////////////////////////////////////// */
Program_I2Smode_SPORT0_Registers:
/* sport0 receive control register */
R0 = 0x013D09F1; /* slave mode, slen = 32 , spen_A, sden_A & schen_A enabled, spen_B, sden_B & schen_B enabled */
dm(SRCTL0) = R0; /* sport 0 receive control register */
/* sport0 transmit control register */
R0 = 0x013D0DF1; /* master mode, data depend, slen = 32, spen_A, sden_A & schen_A enabled, spen_B, sden_B & schen_B enabled */
dm(STCTL0) = R0; /* sport 0 transmit control register */
/* sport0 I2S word select (transmit frame sync) divide register...
We want to set up a frame sync of 96KHz, since this is twice of 48 KHz
Data coming from the AD1819a is 48 KHz, so to send both left and right data via the
I2S ports, we need to send the stereo data at a rate = 2x of the AD1819a Fs. The TFS will
toggle every 96 K, but both left and right I2S data is being transmitted at a rate of 48K equivalent
to the AD1819a frame rate
The SPORT0 ISR will be called at a rate of 48K since the I2S DMA buffers are 2 words deep
*/
R0 = 0x007C0004; /* TCLKDIV=[2xfCLKIN(60MHz)/SCLKfreq(12MHz)]-1 = 0x0004v */
dm(TDIV0) = R0; /* TFSDIV=[TCLKfrq(12 MHz)/TFSfrq(96.0K)]-1 = 124 = 0x007C */
/* sport0 I2S receive word select divide register */
R0 = 0x00000000;
dm(RDIV0) = R0;
/* sport0 receive and transmit multichannel word enable registers */
R0 = 0x00000000; /* multichannel mode disabled */
dm(MRCS0) = R0;
dm(MTCS0) = R0;
/* sport0 transmit and receive multichannel companding enable registers */
R0 = 0x00000000; /* no companding */
dm(MRCCS0) = R0; /* no companding on receive */
dm(MTCCS0) = R0; /* no companding on transmit */
RTS;
/* //////////////////////////////////////////////////////////////////////////////// */
/* DMA Controller Programming For SPORT0 I2S Mode Tx and Rx */
/* */
/* Setup SPORT0 I2S Mode A and B channels for DMA Chaining: */
/* //////////////////////////////////////////////////////////////////////////////// */
Program_DMA_Controller_SPT0:
r1 = 0x0001FFFF; /* cpx register mask */
/* sport0 dma control tx chain pointer register */
r0 = tx0a_buf;
dm(xmit0a_tcb + 7) = r0; /* internal dma address used for chaining*/
r0 = 1;
dm(xmit0a_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 2;
dm(xmit0a_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = xmit0a_tcb + 7; /* get DMA chaining internal mem pointer containing tx_buf address */
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(xmit0a_tcb + 4) = r0; /* write DMA transmit block chain pointer to TCB buffer */
dm(CPT0A) = r0; /* transmit block chain pointer, initiate tx0 DMA transfers */
/* sport0 dma control rx chain pointer register */
r0 = rx0a_buf;
dm(rcv0a_tcb + 7) = r0; /* internal dma address used for chaining */
r0 = 1;
dm(rcv0a_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 2;
dm(rcv0a_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = rcv0a_tcb + 7;
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(rcv0a_tcb + 4) = r0; /* write DMA receive block chain pointer to TCB buffer*/
dm(CPR0A) = r0; /* receive block chain pointer, initiate rx0 DMA transfers */
/* sport0 dma channel b control tx chain pointer register */
r0 = tx0b_buf;
dm(xmit0b_tcb + 7) = r0; /* internal dma address used for chaining*/
r0 = 1;
dm(xmit0b_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 8;
dm(xmit0b_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = xmit0b_tcb + 7; /* get DMA chaining internal mem pointer containing tx_buf address */
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(xmit0b_tcb + 4) = r0; /* write DMA transmit block chain pointer to TCB buffer */
dm(CPT0B) = r0; /* transmit block chain pointer, initiate tx0 DMA transfers */
/* sport0 dma channel b control rx chain pointer register */
r0 = rx0b_buf;
dm(rcv0b_tcb + 7) = r0; /* internal dma address used for chaining */
r0 = 1;
dm(rcv0b_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 8;
dm(rcv0b_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = rcv0b_tcb + 7;
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(rcv0b_tcb + 4) = r0; /* write DMA receive block chain pointer to TCB buffer*/
dm(CPR0B) = r0; /* receive block chain pointer, initiate rx0 DMA transfers */
RTS;
.endseg;
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