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* | | | | | compensation node
* | | | | | |
.SUBCKT AD829S 1 2 99 50 30 12
*
* INPUT STAGE & POLE AT 200 MHZ
*
R1 2 3 17.8E3
R2 1 3 17.8E3
R3 5 99 56.4
R4 6 99 56.4
CIN 1 2 5E-12
C2 5 6 7.18E-12
I1 4 50 1.2E-3
IOS 1 2 250E-9
EOS 9 1 POLY(1) 19 23 0.5E-3 1
Q1 5 2 10 QX
Q2 6 9 11 QX
R5 10 4 13.4
R6 11 4 13.4
*
EREF 98 0 23 0 1
*
* GAIN STAGE & DOMINANT POLE AT 2.7 KHZ
*
R7 12 98 2.82E6
C3 12 98 5.2E-12
G1 98 12 5 6 17.73E-3
V2 99 13 3.4
V3 14 50 3.4
D3 12 13 DX
D4 14 12 DX
*
* ZERO/POLE PAIR AT 50MHz/100MHz
*
R8 15 16 1E6
R9 16 98 1E6
L1 16 98 1.59E-3
G2 98 15 12 23 1E-6
*
* POLE AT 400 MHZ
*
R41 41 98 1E6
C41 41 98 398E-18
G41 98 41 15 23 1E-6
*
* POLE AT 400 MHZ
*
R42 42 98 1E6
C42 42 98 398E-18
G42 98 42 41 23 1E-6
*
* POLE AT 200 MHZ
*
R43 43 98 1E6
C43 43 98 796E-18
G43 98 43 42 23 1E-6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ
*
R11 18 19 1E6
C6 18 19 5.31E-12
R12 19 98 1
E2 18 98 3 23 10
*
* POLE AT 400 MHZ
*
R15 22 98 1E6
C8 22 98 398E-18
G3 98 22 43 23 1E-6
*
* OUTPUT STAGE
*
RF 25 60 500
CF 60 12 12.5E-12
R16 23 99 100E3
R17 23 50 100E3
ISY 99 50 5.45E-3
R18 25 99 30
R19 25 50 30
L2 25 30 1E-8
G4 28 50 22 25 33.33E-3
G5 29 50 25 22 33.33E-3
G6 25 99 99 22 33.33E-3
G7 50 25 22 50 33.33E-3
V4 26 25 -0.2
V5 25 27 -0.2
D5 22 26 DX
D6 27 22 DX
D7 99 28 DX
D8 99 29 DX
D9 50 28 DY
D10 50 29 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=85.7)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD844 SPICE Macro-model 7/91, Rev. A
* JCB / PMI
*
*
* Copyright 1991 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD844 1 2 99 50 28 12
*
* INPUT STAGE
*
R1 99 8 1E3
R2 10 50 1E3
V1 99 9 11
D1 9 8 DX
V2 11 50 11
D2 10 11 DX
I1 99 5 258E-6
I2 4 50 258E-6
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 6 30 QN
Q4 10 7 30 QP
R3 5 6 300E3
R4 4 7 300E3
*C1 99 6 8.8E-15
*C2 50 7 8.8E-15
*
* INPUT ERROR SOURCES
*
GB1 99 1 POLY(1) 1 22 150E-9 90E-9
GB2 99 30 POLY(1) 1 22 200E-9 90E-9
VOS 3 1 50E-6
LS1 30 2 1E-8
CS1 99 2 1E-12
CS2 50 2 1E-12
*
EREF 97 0 22 0 1
*
* GAIN STAGE & DOMINANT POLE
*
R5 12 97 3E6
C3 12 97 5.5E-12
G1 97 12 99 8 1E-3
G2 12 97 10 50 1E-3
V3 99 13 4.3
V4 14 50 4.3
D3 12 13 DX
D4 14 12 DX
*
* POLE AT 70 MHZ
*
R8 17 97 1E6
C4 17 97 3.18E-15
G4 97 17 12 22 1E-6
*
* POLE AT 300 MHZ
*
R12 21 97 1E6
C8 21 97 0.318E-15
G8 97 21 17 22 1E-6
*
* OUTPUT STAGE
*
ISY 99 50 5.1E-3
R13 22 99 16.7E3
R14 22 50 16.7E3
R15 27 99 30
R16 27 50 30
L2 27 28 6E-8
G9 25 50 21 27 33.33E-3
G10 26 50 27 21 33.33E-3
G11 27 99 99 21 33.33E-3
G12 50 27 21 50 33.33E-3
V5 23 27 0.5
V6 27 24 0.5
D5 21 23 DX
D6 24 21 DX
D7 99 25 DX
D8 99 26 DX
D9 50 25 DY
D10 50 26 DY
*
* MODELS USED
*
.MODEL QN NPN(BF=1E9 IS=1E-15)
.MODEL QP PNP(BF=1E9 IS=1E-15)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD844A SPICE Macro-model 7/91, Rev. A
* JCB / PMI
*
*
* This version of the AD844 model simulates the worst case
* parameters of the 'A' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1991 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD844A 1 2 99 50 28 12
*
* INPUT STAGE
*
R1 99 8 1E3
R2 10 50 1E3
V1 99 9 6.6
D1 9 8 DX
V2 11 50 6.6
D2 10 11 DX
I1 99 5 200E-6
I2 4 50 200E-6
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 6 30 QN
Q4 10 7 30 QP
R3 5 6 300E3
R4 4 7 300E3
C1 99 6 8.8E-15
C2 50 7 8.8E-15
*
* INPUT ERROR SOURCES
*
GB1 99 1 POLY(1) 1 22 400E-9 150E-9
GB2 99 30 POLY(1) 1 22 450E-9 160E-9
VOS 3 1 300E-6
LS1 30 2 1E-8
CS1 99 2 1E-12
CS2 50 2 1E-12
*
EREF 97 0 22 0 1
*
* GAIN STAGE & DOMINANT POLE
*
R5 12 97 2.2E6
C3 12 97 5.5E-12
G1 97 12 99 8 1E-3
G2 12 97 10 50 1E-3
V3 99 13 5.3
V4 14 50 5.3
D3 12 13 DX
D4 14 12 DX
*
* POLE AT 70 MHZ
*
R8 17 97 1E6
C4 17 97 3.18E-15
G4 97 17 12 22 1E-6
*
* POLE AT 300 MHZ
*
R12 21 97 1E6
C8 21 97 0.318E-15
G8 97 21 17 22 1E-6
*
* OUTPUT STAGE
*
ISY 99 50 6.1E-3
R13 22 99 16.7E3
R14 22 50 16.7E3
R15 27 99 30
R16 27 50 30
L2 27 28 6E-8
G9 25 50 21 27 33.33E-3
G10 26 50 27 21 33.33E-3
G11 27 99 99 21 33.33E-3
G12 50 27 21 50 33.33E-3
V5 23 27 0.5
V6 27 24 0.5
D5 21 23 DX
D6 24 21 DX
D7 99 25 DX
D8 99 26 DX
D9 50 25 DY
D10 50 26 DY
*
* MODELS USED
*
.MODEL QN NPN(BF=1E9 IS=1E-15)
.MODEL QP PNP(BF=1E9 IS=1E-15)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD844B SPICE Macro-model 7/91, Rev. A
* JCB / PMI
*
*
* This version of the AD844 model simulates the worst case
* parameters of the 'B' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1991 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD844B 1 2 99 50 28 12
*
* INPUT STAGE
*
R1 99 8 1E3
R2 10 50 1E3
V1 99 9 6.6
D1 9 8 DX
V2 11 50 6.6
D2 10 11 DX
I1 99 5 200E-6
I2 4 50 200E-6
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 6 30 QN
Q4 10 7 30 QP
R3 5 6 300E3
R4 4 7 300E3
C1 99 6 8.8E-15
C2 50 7 8.8E-15
*
* INPUT ERROR SOURCES
*
GB1 99 1 POLY(1) 1 22 200E-9 120E-9
GB2 99 30 POLY(1) 1 22 250E-9 110E-9
VOS 3 1 150E-6
LS1 30 2 1E-8
CS1 99 2 1E-12
CS2 50 2 1E-12
*
EREF 97 0 22 0 1
*
* GAIN STAGE & DOMINANT POLE
*
R5 12 97 2.8E6
C3 12 97 5.5E-12
G1 97 12 99 8 1E-3
G2 12 97 10 50 1E-3
V3 99 13 5.3
V4 14 50 5.3
D3 12 13 DX
D4 14 12 DX
*
* POLE AT 70 MHZ
*
R8 17 97 1E6
C4 17 97 3.18E-15
G4 97 17 12 22 1E-6
*
* POLE AT 300 MHZ
*
R12 21 97 1E6
C8 21 97 0.318E-15
G8 97 21 17 22 1E-6
*
* OUTPUT STAGE
*
ISY 99 50 6.1E-3
R13 22 99 16.7E3
R14 22 50 16.7E3
R15 27 99 30
R16 27 50 30
L2 27 28 6E-8
G9 25 50 21 27 33.33E-3
G10 26 50 27 21 33.33E-3
G11 27 99 99 21 33.33E-3
G12 50 27 21 50 33.33E-3
V5 23 27 0.5
V6 27 24 0.5
D5 21 23 DX
D6 24 21 DX
D7 99 25 DX
D8 99 26 DX
D9 50 25 DY
D10 50 26 DY
*
* MODELS USED
*
.MODEL QN NPN(BF=1E9 IS=1E-15)
.MODEL QP PNP(BF=1E9 IS=1E-15)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD844S SPICE Macro-model 7/91, Rev. A
* JCB / PMI
*
*
* This version of the AD844 model simulates the worst case
* parameters of the 'S' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1991 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD844S 1 2 99 50 28 12
*
* INPUT STAGE
*
R1 99 8 1E3
R2 10 50 1E3
V1 99 9 6.6
D1 9 8 DX
V2 11 50 6.6
D2 10 11 DX
I1 99 5 200E-6
I2 4 50 200E-6
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 6 30 QN
Q4 10 7 30 QP
R3 5 6 300E3
R4 4 7 300E3
C1 99 6 8.8E-15
C2 50 7 8.8E-15
*
* INPUT ERROR SOURCES
*
GB1 99 1 POLY(1) 1 22 400E-9 150E-9
GB2 99 30 POLY(1) 1 22 450E-9 160E-9
VOS 3 1 300E-6
LS1 30 2 1E-8
CS1 99 2 1E-12
CS2 50 2 1E-12
*
EREF 97 0 22 0 1
*
* GAIN STAGE & DOMINANT POLE
*
R5 12 97 2.2E6
C3 12 97 5.5E-12
G1 97 12 99 8 1E-3
G2 12 97 10 50 1E-3
V3 99 13 5.3
V4 14 50 5.3
D3 12 13 DX
D4 14 12 DX
*
* POLE AT 70 MHZ
*
R8 17 97 1E6
C4 17 97 3.18E-15
G4 97 17 12 22 1E-6
*
* POLE AT 300 MHZ
*
R12 21 97 1E6
C8 21 97 0.318E-15
G8 97 21 17 22 1E-6
*
* OUTPUT STAGE
*
ISY 99 50 6.1E-3
R13 22 99 16.7E3
R14 22 50 16.7E3
R15 27 99 30
R16 27 50 30
L2 27 28 6E-8
G9 25 50 21 27 33.33E-3
G10 26 50 27 21 33.33E-3
G11 27 99 99 21 33.33E-3
G12 50 27 21 50 33.33E-3
V5 23 27 0.5
V6 27 24 0.5
D5 21 23 DX
D6 24 21 DX
D7 99 25 DX
D8 99 26 DX
D9 50 25 DY
D10 50 26 DY
*
* MODELS USED
*
.MODEL QN NPN(BF=1E9 IS=1E-15)
.MODEL QP PNP(BF=1E9 IS=1E-15)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD846 SPICE Macro-model 1/91, Rev. A
* JCB / PMI
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation pin
* | | | | | |
.SUBCKT AD846 1 2 99 50 28 12
*
* INPUT STAGE
*
R1 99 8 1E3
R2 10 50 1E3
V1 99 9 1.7
D1 9 8 DX
V2 11 50 1.7
D2 10 11 DX
I1 99 5 275E-6
I2 4 50 275E-6
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 6 30 QN
Q4 10 7 30 QP
R3 5 6 300E3
R4 4 7 300E3
*
* INPUT ERROR SOURCES
*
GB1 99 1 POLY(1) 1 22 3E-6 5E-9
GB2 99 30 POLY(1) 1 22 150E-9 5E-9
VOS 3 1 25E-6
LS1 30 2 50E-9
CS1 99 2 2.0E-12
CS2 99 1 2.0E-12
*
EREF 97 0 22 0 1
*
* TRANSCONDUCTANCE STAGE
*
R5 12 97 200E6
C3 12 97 5.5E-12
G1 97 12 99 8 1E-3
G2 12 97 10 50 1E-3
V3 99 13 1.3
V4 14 50 1.3
D3 12 13 DX
D4 14 12 DX
*
* POLE AT 100 MHZ
*
R8 17 97 1E6
C4 17 97 1.59E-15
G4 97 17 12 22 1E-6
*
* POLE AT 100 MHZ
*
R9 18 97 1E6
C5 18 97 1.59E-15
G5 97 18 17 22 1E-6
*
* POLE AT 200 MHZ
*
R10 19 97 1E6
C6 19 97 0.795E-15
G6 97 19 18 22 1E-6
*
* POLE AT 500 MHZ
*
R11 20 97 1E6
C7 20 97 0.318E-15
G7 97 20 19 22 1E-6
*
* POLE AT 500 MHZ
*
R12 21 97 1E6
C8 21 97 0.318E-15
G8 97 21 20 22 1E-6
*
* OUTPUT STAGE
*
ISY 99 50 3.55E-3
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