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* was developed using the +-5V specifications.
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.
* Use of this model indicates your acceptance with
* the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | DISABLE pin
* | | | | | |
.SUBCKT AD810A 1 2 99 50 41 33
*
* INPUT STAGE
*
R1 99 8 680
R2 10 50 680
V1 99 9 0.5
D1 9 8 DX
V2 11 50 0.5
D2 10 11 DX
F1 99 5 VD2 1
F2 4 50 VD2 1
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 5 2 QN
Q4 10 4 2 QP
R3 99 5 0.4E8
R4 50 4 0.4E8
*
* INPUT ERROR SOURCES
*
GB1 1 99 POLY(1) (1,22) 7.5E-6 0.1E-6
GB2 2 99 POLY(1) (1,22) 5E-6 0.1E-6
EOS 3 1 POLY(1) (17,22) 6E-3 25.119E-3
CS1 99 2 0.75E-12
CS2 99 1 2E-12
*
* TRANSCONDUCTANCE STAGE
*
EREF 98 0 (22,0) 1
R5 12 98 0.3E6
C3 12 98 4.15E-12
G1 98 12 (99,8) 1.471E-3
G2 12 98 (10,50) 1.471E-3
V3 99 13 3
V4 14 50 3
D3 12 13 DX
D4 14 12 DX
*
* COMMON MODE STAGE WITH ZERO AT 2.512MHZ
*
E2 16 98 (1,22) 1
R12 16 17 10
R13 17 98 1
C6 16 17 12.672E-9
*
* POLE AT 90MHZ
*
R6 21 98 1E6
C4 21 98 1.768E-15
G3 98 21 (12,22) 1E-6
*
* OUTPUT STAGE
*
FSY 99 50 POLY(1) VD2 2.177E-3 2.707
FSY1 99 0 V7 1
FSY2 0 50 V8 1
R9 22 99 40.625E3
R10 22 50 40.625E3
E1 25 98 21 22 1
H1 26 25 POLY(1) VD3 0.7 10E3
H2 25 27 POLY(1) VD3 0.7 10E3
RH1 40 50 1E10
R7 28 40 10
R8 40 29 10
D7 26 28 DX
D8 29 27 DX
VS 40 41 DC 0
CL 41 50 10E-12
V5 23 40 0.5
V6 40 24 0.5
D5 21 23 DX
D6 24 21 DX
F10 98 70 VS 1
D9 70 71 DX
D10 72 70 DX
V7 71 98 DC 0
V8 98 72 DC 0
*
* DISABLE FUNCTION
*
VD1 99 31 DC 1.8
RD1 31 32 35E3
RD2 33 99 1E12
DD1 32 33 DX
FD 98 34 POLY(1) VD1 0.8E-3 -18.0203
DD3 36 34 DX
DD2 34 35 DX
VD2 37 98 DC 0
VD3 38 98 DC 0
RD3 35 37 1E3
RD4 36 38 1E3
CD1 34 98 10E-12
*
* MODELS USED
*
.MODEL QN NPN(BF=200 IS=1E-15)
.MODEL QP PNP(BF=200 IS=1E-15)
.MODEL DX D(IS=1E-15)
.ENDS AD810A* AD810S SPICE Macro-model 12/93, Rev. A
* ARG / PMI
*
* This version of the AD810 model simulates the worst-case
* parameters of the 'S' grade. The worst-case parameters
* used correspond to those in the data sheet. This model
* was developed using the +-5V specifications.
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.
* Use of this model indicates your acceptance with
* the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | DISABLE pin
* | | | | | |
.SUBCKT AD810S 1 2 99 50 41 33
*
* INPUT STAGE
*
R1 99 8 680
R2 10 50 680
V1 99 9 0.5
D1 9 8 DX
V2 11 50 0.5
D2 10 11 DX
F1 99 5 VD2 1
F2 4 50 VD2 1
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 5 2 QN
Q4 10 4 2 QP
R3 99 5 0.4E8
R4 50 4 0.4E8
*
* INPUT ERROR SOURCES
*
GB1 1 99 POLY(1) (1,22) 7.5E-6 0.1E-6
GB2 2 99 POLY(1) (1,22) 5E-6 0.1E-6
EOS 3 1 POLY(1) (17,22) 6E-3 25.119E-3
CS1 99 2 0.75E-12
CS2 99 1 2E-12
*
* TRANSCONDUCTANCE STAGE
*
EREF 98 0 (22,0) 1
R5 12 98 0.3E6
C3 12 98 4.15E-12
G1 98 12 (99,8) 1.471E-3
G2 12 98 (10,50) 1.471E-3
V3 99 13 3
V4 14 50 3
D3 12 13 DX
D4 14 12 DX
*
* COMMON MODE STAGE WITH ZERO AT 2.512MHZ
*
E2 16 98 (1,22) 1
R12 16 17 10
R13 17 98 1
C6 16 17 6.336E-9
*
* POLE AT 90MHZ
*
R6 21 98 1E6
C4 21 98 1.768E-15
G3 98 21 (12,22) 1E-6
*
* OUTPUT STAGE
*
FSY 99 50 POLY(1) VD2 2.177E-3 2.707
FSY1 99 0 V7 1
FSY2 0 50 V8 1
R9 22 99 40.625E3
R10 22 50 40.625E3
E1 25 98 21 22 1
H1 26 25 POLY(1) VD3 0.7 10E3
H2 25 27 POLY(1) VD3 0.7 10E3
RH1 40 50 1E10
R7 28 40 10
R8 40 29 10
D7 26 28 DX
D8 29 27 DX
VS 40 41 DC 0
CL 41 50 10E-12
V5 23 40 0.5
V6 40 24 0.5
D5 21 23 DX
D6 24 21 DX
F10 98 70 VS 1
D9 70 71 DX
D10 72 70 DX
V7 71 98 DC 0
V8 98 72 DC 0
*
* DISABLE FUNCTION
*
VD1 99 31 DC 1.8
RD1 31 32 35E3
RD2 33 99 1E12
DD1 32 33 DX
FD 98 34 POLY(1) VD1 0.8E-3 -18.0203
DD3 36 34 DX
DD2 34 35 DX
VD2 37 98 DC 0
VD3 38 98 DC 0
RD3 35 37 1E3
RD4 36 38 1E3
CD1 34 98 10E-12
*
* MODELS USED
*
.MODEL QN NPN(BF=200 IS=1E-15)
.MODEL QP PNP(BF=200 IS=1E-15)
.MODEL DX D(IS=1E-15)
.ENDS AD810S* AD811 SPICE Macro-model 7/91, Rev. A
* JCB / PMI
*
* Copyright 1990 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD829 1 2 99 50 30 12
*
* INPUT STAGE & POLE AT 200 MHZ
*
R1 2 3 17.8E3
R2 1 3 17.8E3
R3 5 99 56.4
R4 6 99 56.4
CIN 1 2 5E-12
C2 5 6 7.18E-12
I1 4 50 1.2E-3
IOS 1 2 25E-9
EOS 9 1 POLY(1) 19 23 0.2E-3 1
Q1 5 2 10 QX
Q2 6 9 11 QX
R5 10 4 13.4
R6 11 4 13.4
*
EREF 98 0 23 0 1
*
* GAIN STAGE & DOMINANT POLE AT 5.4 KHZ
*
R7 12 98 5.64E6
C3 12 98 5.2E-12
G1 98 12 5 6 17.73E-3
V2 99 13 2.1
V3 14 50 2.1
D3 12 13 DX
D4 14 12 DX
*
* ZERO/POLE PAIR AT 50MHz/100MHz
*
R8 15 16 1E6
R9 16 98 1E6
L1 16 98 1.59E-3
G2 98 15 12 23 1E-6
*
* POLE AT 400 MHZ
*
R41 41 98 1E6
C41 41 98 398E-18
G41 98 41 15 23 1E-6
*
* POLE AT 400 MHZ
*
R42 42 98 1E6
C42 42 98 398E-18
G42 98 42 41 23 1E-6
*
* POLE AT 200 MHZ
*
R43 43 98 1E6
C43 43 98 796E-18
G43 98 43 42 23 1E-6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 3 kHZ
*
R11 18 19 1E6
C6 18 19 53.1E-12
R12 19 98 1
E2 18 98 3 23 1
*
* POLE AT 400 MHZ
*
R15 22 98 1E6
C8 22 98 398E-18
G3 98 22 43 23 1E-6
*
* OUTPUT STAGE
*
RF 25 60 500
CF 60 12 12.5E-12
R16 23 99 100E3
R17 23 50 100E3
ISY 99 50 3.95E-3
R18 25 99 30
R19 25 50 30
L2 25 30 1E-8
G4 28 50 22 25 33.33E-3
G5 29 50 25 22 33.33E-3
G6 25 99 99 22 33.33E-3
G7 50 25 22 50 33.33E-3
V4 26 25 -0.2
V5 25 27 -0.2
D5 22 26 DX
D6 27 22 DX
D7 99 28 DX
D8 99 29 DX
D9 50 28 DY
D10 50 29 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=181.8)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD829A SPICE Macro-model 9/90, Rev. A
* JCB / PMI
*
* This version of the AD829 model simulates the worst case
* parameters of the 'A' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1990 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD829A 1 2 99 50 30 12
*
* INPUT STAGE & POLE AT 200 MHZ
*
R1 2 3 17.8E3
R2 1 3 17.8E3
R3 5 99 56.4
R4 6 99 56.4
CIN 1 2 5E-12
C2 5 6 7.18E-12
I1 4 50 1.2E-3
IOS 1 2 250E-9
EOS 9 1 POLY(1) 19 23 0.5E-3 1
Q1 5 2 10 QX
Q2 6 9 11 QX
R5 10 4 13.4
R6 11 4 13.4
*
EREF 98 0 23 0 1
*
* GAIN STAGE & DOMINANT POLE AT 2.7 KHZ
*
R7 12 98 2.82E6
C3 12 98 5.2E-12
G1 98 12 5 6 17.73E-3
V2 99 13 3.4
V3 14 50 3.4
D3 12 13 DX
D4 14 12 DX
*
* ZERO/POLE PAIR AT 50MHz/100MHz
*
R8 15 16 1E6
R9 16 98 1E6
L1 16 98 1.59E-3
G2 98 15 12 23 1E-6
*
* POLE AT 400 MHZ
*
R41 41 98 1E6
C41 41 98 398E-18
G41 98 41 15 23 1E-6
*
* POLE AT 400 MHZ
*
R42 42 98 1E6
C42 42 98 398E-18
G42 98 42 41 23 1E-6
*
* POLE AT 200 MHZ
*
R43 43 98 1E6
C43 43 98 796E-18
G43 98 43 42 23 1E-6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ
*
R11 18 19 1E6
C6 18 19 5.31E-12
R12 19 98 1
E2 18 98 3 23 10
*
* POLE AT 400 MHZ
*
R15 22 98 1E6
C8 22 98 398E-18
G3 98 22 43 23 1E-6
*
* OUTPUT STAGE
*
RF 25 60 500
CF 60 12 12.5E-12
R16 23 99 100E3
R17 23 50 100E3
ISY 99 50 5.45E-3
R18 25 99 30
R19 25 50 30
L2 25 30 1E-8
G4 28 50 22 25 33.33E-3
G5 29 50 25 22 33.33E-3
G6 25 99 99 22 33.33E-3
G7 50 25 22 50 33.33E-3
V4 26 25 -0.2
V5 25 27 -0.2
D5 22 26 DX
D6 27 22 DX
D7 99 28 DX
D8 99 29 DX
D9 50 28 DY
D10 50 29 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=85.7)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD829J SPICE Macro-model 9/90, Rev. A
* JCB / PMI
*
* This version of the AD829 model simulates the worst case
* parameters of the 'J' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1990 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | compensation node
* | | | | | |
.SUBCKT AD829J 1 2 99 50 30 12
*
* INPUT STAGE & POLE AT 200 MHZ
*
R1 2 3 17.8E3
R2 1 3 17.8E3
R3 5 99 56.4
R4 6 99 56.4
CIN 1 2 5E-12
C2 5 6 7.18E-12
I1 4 50 1.2E-3
IOS 1 2 250E-9
EOS 9 1 POLY(1) 19 23 1.0E-3 1
Q1 5 2 10 QX
Q2 6 9 11 QX
R5 10 4 13.4
R6 11 4 13.4
*
EREF 98 0 23 0 1
*
* GAIN STAGE & DOMINANT POLE AT 2.7 KHZ
*
R7 12 98 2.82E6
C3 12 98 5.2E-12
G1 98 12 5 6 17.73E-3
V2 99 13 3.4
V3 14 50 3.4
D3 12 13 DX
D4 14 12 DX
*
* ZERO/POLE PAIR AT 50MHz/100MHz
*
R8 15 16 1E6
R9 16 98 1E6
L1 16 98 1.59E-3
G2 98 15 12 23 1E-6
*
* POLE AT 400 MHZ
*
R41 41 98 1E6
C41 41 98 398E-18
G41 98 41 15 23 1E-6
*
* POLE AT 400 MHZ
*
R42 42 98 1E6
C42 42 98 398E-18
G42 98 42 41 23 1E-6
*
* POLE AT 200 MHZ
*
R43 43 98 1E6
C43 43 98 796E-18
G43 98 43 42 23 1E-6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ
*
R11 18 19 1E6
C6 18 19 5.31E-12
R12 19 98 1
E2 18 98 3 23 10
*
* POLE AT 400 MHZ
*
R15 22 98 1E6
C8 22 98 398E-18
G3 98 22 43 23 1E-6
*
* OUTPUT STAGE
*
RF 25 60 500
CF 60 12 12.5E-12
R16 23 99 100E3
R17 23 50 100E3
ISY 99 50 5.45E-3
R18 25 99 30
R19 25 50 30
L2 25 30 1E-8
G4 28 50 22 25 33.33E-3
G5 29 50 25 22 33.33E-3
G6 25 99 99 22 33.33E-3
G7 50 25 22 50 33.33E-3
V4 26 25 -0.2
V5 25 27 -0.2
D5 22 26 DX
D6 27 22 DX
D7 99 28 DX
D8 99 29 DX
D9 50 28 DY
D10 50 29 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=85.7)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS
* AD829S SPICE Macro-model 9/90, Rev. A
* JCB / PMI
*
* This version of the AD829 model simulates the worst case
* parameters of the 'S' grade. The worst case parameters
* used correspond to those in the data sheet.
*
* Copyright 1990 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
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