analog.lib

通信原理-高频电子电路CAI-340页-22.2M-ppt版.zip

* Copyright 1994 by Analog Devices, Inc.
*
*AD8001A SPICE Macro Model       9/94, Rev. A
* AAG/ADSC
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License
* Statement
*
* Node assignments
*               Non-inverting input
*               | Inverting input
*               | | Positive supply
*               | | | Negative supply
*               | | | | Output
*               | | | | |
.SUBCKT AD8001A 3 2 7 4 6
*
* INPUT STAGE
*
CIN 3 4 1.5E-12
GB1 7 3 POLY(1) 3 100 (3E-6,0.2E-6)
EOS 9 3 POLY(1) 23 100 (2E-3,1)
Q1 7 9 10 QN
I1 10 4 DC 2.568E-4
I2 7 11 DC 2.568E-4
Q2 4 9 11 QP
R1 7 14 1E3
V1 7 17 DC 6.96561E-2
D1 17 14 DX
Q3 14 11 15 QN
Q4 16 10 15 QP
R2 16 4 1E3
D2 16 18 DX
V2 18 4 DC 6.96561E-2
LIN- 15 2 0.1E-9
GB2 7 2 POLY(1) 3 100 (5E-6,0.3E-6)
CS1 7 2 0.03E-12
CS2 2 4 0.03E-12
*
* GAIN STAGE AND DOMINANT POLE AT 230 kHz
*
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
G1 100 19 7 14 1E-3
G2 19 100 16 4 1E-3
R3 19 100 1.24E6
C1 19 100 5.580468E-13
V3 7 20 DC 2.3747
D3 19 20 DX
D4 21 19 DX
V4 21 4 DC 2.3747
*
* COMMON-MODE REJECTION NETWORK WITH ZERO AT 22 MHz
*
ECM 100 22 3 100 19.95
RCM1 22 23 1E4
CCM 22 23 7.2343E-13
RCM2 23 100 1
*
* POLE AT 800 MHz
*
G4 100 24 19 100 1E-6
R5 24 100 1E6
C3 24 100 1.9894368E-16
*
* POLE AT 4 GHz
*
G5 100 25 24 100 1E-6
R6 25 100 1E6
C4 25 100 3.9788736E-17
*
* OUTPUT STAGE
*
VW 25 30 DC 0
*
FSY 7 4 POLY(2) VSY1 VSY2 (4.2326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
DSY1 35 36 DX
VSY1 36 100 DC 0
DSY2 37 35 DX
VSY2 100 37 DC 0
DSC1 30 31 DX
VSC1 31 33 DC 0.62526
DSC2 32 30 DX
VSC2 33 32 DC 0.62526
GO1 33 7 7 30 4.6728972E-2
RO1 7 33 21.4
GO2 4 33 30 4 4.6728972E-2
RO2 33 4 21.4
LO 33 6 7E-9
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
*
.ENDS AD8001A
*AD8001AN SPICE Macro Model       9/94, Rev. A
*                                 AAG/ADSC
*
* This version of the AD8001 model simulates the worst case 
* parameters of the 'A' grade in the N package (PDIP).  The worst case
* parameters used correspond to those in the data sheet.
* This model was developed using the +-5V specifications.
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License
* Statement
*
* Node assignments
*                Non-inverting input
*                | Inverting input
*                | | Positive supply
*                | | | Negative supply
*                | | | | Output
*                | | | | |
.SUBCKT AD8001AN 3 2 7 4 6
*
* INPUT STAGE
*
CIN 3 4 1.5E-12
GB1 7 3 POLY(1) 3 100 (6E-6,0.3E-6)
EOS 9 3 POLY(1) 23 100 (5E-3,1)
Q1 7 9 10 QN
I1 10 4 DC 2.568E-4
I2 7 11 DC 2.568E-4
Q2 4 9 11 QP
R1 7 14 1E3
V1 7 17 DC -6.34541E-2
D1 17 14 DX
Q3 14 11 15 QN
Q4 16 10 15 QP
R2 16 4 1E3
D2 16 18 DX
V2 18 4 DC -6.34541E-2
LIN- 15 2 0.1E-9
GB2 7 2 POLY(1) 3 100 (25E-6,1E-6)
CS1 7 2 0.03E-12
CS2 2 4 0.03E-12
*
* GAIN STAGE AND DOMINANT POLE AT 891 kHz
*
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
G1 100 19 7 14 1E-3
G2 19 100 16 4 1E-3
R3 19 100 3.196E5
C1 19 100 5.58902E-13
V3 7 20 DC 2.8108
D3 19 20 DX
D4 21 19 DX
V4 21 4 DC 2.8108
*
* COMMON-MODE REJECTION NETWORK WITH ZERO AT 34.87 MHz
*
ECM 100 22 3 100 31.668
RCM1 22 23 1E4
CCM 22 23 4.56424E-13
RCM2 23 100 1
*
* POLE AT 800 MHz
*
G4 100 24 19 100 1E-6
R5 24 100 1E6
C3 24 100 1.9894368E-16
*
* POLE AT 4 GHz
*
G5 100 25 24 100 1E-6
R6 25 100 1E6
C4 25 100 3.9788736E-17
*
* OUTPUT STAGE
*
VW 25 30 DC 0
*
FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
DSY1 35 36 DX
VSY1 36 100 DC 0
DSY2 37 35 DX
VSY2 100 37 DC 0
DSC1 30 31 DX
VSC1 31 33 DC 0.3615
DSC2 32 30 DX
VSC2 33 32 DC 0.3615
GO1 33 7 7 30 4.6728972E-2
RO1 7 33 21.4
GO2 4 33 30 4 4.6728972E-2
RO2 33 4 21.4
LO 33 6 7E-9
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
*
.ENDS AD8001AN
*AD8001AR SPICE Macro Model       9/94, Rev. A
*                                 AAG/ADSC
*
* This version of the AD8001 model simulates the worst case 
* parameters of the 'A' grade in the R package (SOIC).  The worst case
* parameters used correspond to those in the data sheet.
* This model was developed using the +-5V specifications.
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License
* Statement
*
* Node assignments
*                Non-inverting input
*                | Inverting input
*                | | Positive supply
*                | | | Negative supply
*                | | | | Output
*                | | | | |
.SUBCKT AD8001AR 3 2 7 4 6
*
* INPUT STAGE
*
CIN 3 4 1.5E-12
GB1 7 3 POLY(1) 3 100 (6E-6,0.3E-6)
EOS 9 3 POLY(1) 23 100 (5E-3,1)
Q1 7 9 10 QN
I1 10 4 DC 2.568E-4
I2 7 11 DC 2.568E-4
Q2 4 9 11 QP
R1 7 14 1E3
V1 7 17 DC -4.41135E-2
D1 17 14 DX
Q3 14 11 15 QN
Q4 16 10 15 QP
R2 16 4 1E3
D2 16 18 DX
V2 18 4 DC -4.41135E-2
LIN- 15 2 0.1E-9
GB2 7 2 POLY(1) 3 100 (25E-6,1E-6)
CS1 7 2 0.03E-12
CS2 2 4 0.03E-12
*
* GAIN STAGE AND DOMINANT POLE AT 860 kHz
*
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
G1 100 19 7 14 1E-3
G2 19 100 16 4 1E-3
R3 19 100 3.196E5
C1 19 100 5.79048E-13
V3 7 20 DC 2.8108
D3 19 20 DX
D4 21 19 DX
V4 21 4 DC 2.8108
*
* COMMON-MODE REJECTION NETWORK WITH ZERO AT 34.87 MHz
*
ECM 100 22 3 100 31.668
RCM1 22 23 1E4
CCM 22 23 4.56424E-13
RCM2 23 100 1
*
* POLE AT 800 MHz
*
G4 100 24 19 100 1E-6
R5 24 100 1E6
C3 24 100 1.9894368E-16
*
* POLE AT 4 GHz
*
G5 100 25 24 100 1E-6
R6 25 100 1E6
C4 25 100 3.9788736E-17
*
* OUTPUT STAGE
*
VW 25 30 DC 0
*
FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
DSY1 35 36 DX
VSY1 36 100 DC 0
DSY2 37 35 DX
VSY2 100 37 DC 0
DSC1 30 31 DX
VSC1 31 33 DC 0.3615
DSC2 32 30 DX
VSC2 33 32 DC 0.3615
GO1 33 7 7 30 4.6728972E-2
RO1 7 33 21.4
GO2 4 33 30 4 4.6728972E-2
RO2 33 4 21.4
LO 33 6 7E-9
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
*
.ENDS AD8001AR
*AD8002A SPICE Macro Model          11/95, Rev. A
*                                         RFD/ADS
*  
* Copyright 1995 by Analog Devices, Inc.
*
* This version of the AD8002 model simulates the typical 
* parameters of the 'A' grade part.  
*
* This model was developed using the +/-5V specifications.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License  
* Statement.
*
* Node assignments
*               Non-inverting input
*               | Inverting input
*               | | Positive supply
*               | | | Negative supply
*               | | | | Output
*               | | | | |
.SUBCKT AD8002A 3 2 7 4 6 
*
****** INPUT STAGE ******
*
Q1 7 9 10 QN
Q2 4 9 11 QP
Q3 14 11 15 QN
Q4 16 10 15 QP
I1 10 4 DC 2.568e-4 
I2 7 11 DC 2.568e-4 
D1 17 14 DX 
D2 16 18 DX 
V2 18 4 DC -4.41135e-2 
V1 7 17 DC -4.41135e-2 
R1 14 7 1E3 
R2 4 16 1E3 
CS1 7 2 .235e-12 
CS2 2 4 .235e-12 
CIN 3 4 1.5E-12 
LIN- 15 2 .9e-9 
GB1 7 3 POLY(1) 3 100 (3e-6,0.2e-6)
GB2 7 2 POLY(1) 3 100 (5e-6,0.3e-6)
EOS 3 9 POLY(1) 100 23 (2E-3,1)
*
****** GAIN STAGE  ********
*
V3 7 20 DC 2.4 
V4 21 4 DC 2.4 
R3 100 19 9e5 
C1 19 100 6.1e-13 
D3 19 20 DX 
D4 21 19 DX 
G1 100 19 POLY(1) 7 14 (0.0,1E-3)
G2 19 100 POLY(1) 16 4 (0.0,1E-3)
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
*
****** CMRR STAGE ******
*
CCM 22 23 4.56424e-13 
RCM2 100 23 1 
RCM1 23 22 1e4 
ECM 22 100 POLY(1) 100 3 (0.0,31.668)
*
****** POLE STAGE AT   ******
*
C3 100 24 2.273642e-16 
R5 24 100 1e6 
G4 100 24 POLY(1) 19 100 (0.0,1E-6)
*
****** POLE STAGE AT   ******
*
C4 25 100 3.978877e-17 
R6 25 100 1e6 
G5 100 25 POLY(1) 24 100 (0.0,1E-6)
* 
****** OUTPUT STAGE ****** 
* 
RO1 33 7 21.4 
RO2 4 33 21.4 
VW 25 30 DC 0 
VSC1 31 33 DC .58 
VSC2 33 32 DC .58 
LO 33 6 2e-9 
DSC2 32 30 DX 
DSC1 30 31 DX 
GO1 33 7 POLY(1) 7 30 (0.0,4.6728972e-2)
GO2 4 33 POLY(1) 30 4 (0.0,4.6728972e-2)
*
VSY1 36 100 DC 0 
VSY2 100 37 DC 0 
DSY1 35 36 DX 
DSY2 37 35 DX 
FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
.ENDS AD8002A
*AD8002AN SPICE Macro Model        11/95, Rev. A
*                                        RFD/ADS
*  
* This version of the AD8002 model simulates the worst case 
* parameters of the 'A' grade in the 'N ' package (PDIP).  The Worst case
* parameters used correspond to those in the data sheet. 
* This model was developed using the +/-5V specifications.
*
* Copyright 1995 by Analog Devices, Inc.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License  
* Statement.
*
* Node assignments
*                Non-inverting input
*                | Inverting input
*                | | Positive supply
*                | | | Negative supply
*                | | | | Output
*                | | | | |
.SUBCKT AD8002AN 3 2 7 4 6 
*
****** INPUT STAGE ******
*
Q1 7 9 10 QN
Q2 4 9 11 QP
Q3 14 11 15 QN
Q4 16 10 15 QP
I1 10 4 DC 2.568e-4 
I2 7 11 DC 2.568e-4 
D1 17 14 DX 
D2 16 18 DX 
V2 18 4 DC -4.41135e-2 
V1 7 17 DC -4.41135e-2 
R1 14 7 1E3 
R2 4 16 1E3 
CS1 7 2 .25e-12 
CS2 2 4 .25e-12 
CIN 3 4 1.5E-12 
LIN- 15 2 .9e-9 
GB1 7 3 POLY(1) 3 100 (6e-6,0.9e-6)
GB2 7 2 POLY(1) 3 100 (25e-6,1e-6)
EOS 3 9 POLY(1) 100 23 (6E-3,1)
*
****** GAINST  ********
*
V3 7 20 DC 2.8108 
V4 21 4 DC 2.8108 
R3 100 19 3.1e5 
C1  19 100 6.05E-13
D3 19 20 DX 
D4 21 19 DX 
G1 100 19 POLY(1) 7 14 (0.0,1E-3)
G2 19 100 POLY(1) 16 4 (0.0,1E-3)
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
*
******  CMRR  ******
*
CCM 22 23 4.56424e-13 
RCM2 100 23 1 
RCM1 23 22 1e4 
ECM 22 100 POLY(1) 100 3 (0.0,31.668)
*
****** POLE 1  ******
*
C3 100 24 2.273642e-16 
R5 24 100 1e6 
G4 100 24 POLY(1) 19 100 (0.0,1E-6)
*
****** POLE 2  ******
*
C4 25 100 3.978877e-17 
R6 25 100 1e6 
G5 100 25 POLY(1) 24 100 (0.0,1E-6)
*  
******  OUTPUT  ****** 
* 
RO1 33 7 21.4 
RO2 4 33 21.4 
VW 25 30 DC 0 
VSC1 31 33 DC .325 
VSC2 33 32 DC .325 
LO 33 6 2e-9 
DSC2 32 30 DX 
DSC1 30 31 DX 
GO1 33 7 POLY(1) 7 30 (0.0,4.6728972e-2)
GO2 4 33 POLY(1) 30 4 (0.0,4.6728972e-2)
*
VSY1 36 100 DC 0 
VSY2 100 37 DC 0 
DSY1 35 36 DX 
DSY2 37 35 DX 
FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
.ENDS AD8002AN
*AD8002AR SPICE Macro Model        11/95, Rev. A
*                                        RFD/ADS
*  
* This version of the AD8002 model simulates the worst case 
* parameters of the 'A' grade in the 'R ' package (SOIC).  The Worst case
* parameters used correspond to those in the data sheet. 
* This model was developed using the +/-5V specifications.
*
* Copyright 1995 by Analog Devices, Inc.
*
* Refer to the "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License  
* Statement.
*
* Node assignments
*                Non-inverting input
*                | Inverting input
*                | | Positive supply
*                | | | Negative supply
*                | | | | Output
*                | | | | |
.SUBCKT AD8002AR 3 2 7 4 6
*
****** INPUT STAGE ********
*
Q1 7 9 10 QN
Q2 4 9 11 QP
Q3 14 11 15 QN
Q4 16 10 15 QP
I1 10 4 DC 2.568e-4 
I2 7 11 DC 2.568e-4 
D1 17 14 DX 
D2 16 18 DX 
V2 18 4 DC -4.41135e-2 
V1 7 17 DC -4.41135e-2 
R1 14 7 1E3 
R2 4 16 1E3 
CS1 7 2 .25e-12 
CS2 2 4 .25e-12 
CIN 3 4 1.5E-12 
LIN- 15 2 .9e-9 
GB1 7 3 POLY(1) 3 100 (6e-6,0.9e-6)
GB2 7 2 POLY(1) 3 100 (25e-6,1e-6)
EOS 3 9 POLY(1) 100 23 (6E-3,1)
*
****** gainst *******
*
V3 7 20 DC 2.8108 
V4 21 4 DC 2.8108 
R3 100 19 3.1e5 
C1 19 100 6.4987781e-13 
D3 19 20 DX 
D4 21 19 DX 
G1 100 19 POLY(1) 7 14 (0,1E-3)
G2 19 100 POLY(1) 16 4 (0,1E-3)
EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5)
*
****** CMRR *********
*
CCM 22 23 4.56424e-13 
RCM2 100 23 1 
RCM1 23 22 1e4 
ECM 22 100 100 3 31.668
*
******* POLE1 ***********
*
C3 100 24 2.273644e-16 
R5 24 100 1e6 
G4 100 24 19 100 1E-6
*
******** POLE2 ***********
*
C4 25 100 3.978877e-17 
R6 25 100 1e6 
G5 100 25 24 100 1E-6
*
****** OUTPUT ********
*
RO1 33 7 21.4 
RO2 4 33 21.4 
VW 25 30 DC 0 
VSC1 31 33 DC .325 
VSC2 33 32 DC .325 
LO 33 6 2e-9 
DSC2 32 30 DX 
DSC1 30 31 DX 
GO1 33 7 POLY(1) 7 30 (0.0, 4.6728972e-2)
GO2 4 33 POLY(1) 30 4 (0.0, 4.6728972e-2)
*
VSY1 36 100 DC 0 
VSY2 100 37 DC 0 
DSY1 35 36 DX 
DSY2 37 35 DX 
FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1)
GSY 100 35 33 30 4.6728972E-2
*
.MODEL QN NPN(BF=100 IS=1E-15)
.MODEL QP PNP(BF=100 IS=1E-15)
.MODEL DX D(IS=1E-15)
.ENDS AD8002AR
* AD645 SPICE Macro-model                   4/92, Rev. B
*                                           JCB / PMI
*
* Revision History:
*     Rev. B:  Converted model to include noise analysis. 
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.  Use of this model