national.lib

通信原理-高频电子电路CAI-340页-22.2M-ppt版.zip

*
*Features:
*Fast settling time (.01%) =           2uS
*High bandwidth =                     3MHz
*High slew rate =                   10V/uS
*Low offset voltage =                 .5mV
*Low supply current =                1.8mA
*
****************INPUT STAGE************** 
*
IOS 2 1 25.0P
*^Input offset current
CI1 1 0 3P
CI2 2 0 3P
R1 1 3 5E11
R2 3 2 5E11
I1 99 4 1.0M
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 650
R4 6 50 650
*Fp2=28 MHZ
C4 5 6 4.372P 
*
***********COMMON MODE EFFECT***********
*
I2 99 50 800UA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 .8E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 20E-3
R5 98 9 10MEG
VA3 9 11 0
*Fp1=18 HZ
C3 98 11 857.516P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.305E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 144.7M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6  99 50 VA7 1
F5  99 23 VA8 1
D5  21 23 DX
VA7 99 21 0
D6  23 99 DX
E1  99 26 99 15 1
VA8 26 27 0
R16 27 28 50
V5  28 25 0.646V
D4  25 15 DX
V4  24 28 0.646V
D3  15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
*
.ENDS
*//////////////////////////////////////////////////////////
*LF412/A LOW OFFSET, LOW DRIFT DUAL JFET INPUT OP-AMP MODEL
*//////////////////////////////////////////////////////////
*
* connections:    non-inverting input
*                 |   inverting input
*                 |   |   positive power supply
*                 |   |   |   negative power supply
*                 |   |   |   |   output
*                 |   |   |   |   |
*                 |   |   |   |   |
.SUBCKT LF412     1   2  99  50  28
*
*Features:
*Fast settling time (.01%) =           2uS
*High bandwidth =                     3MHz
*High slew rate =                   10V/uS
*Low offset voltage =                  1mV
*Low supply current =                1.8mA
*NOTE: Model is for single device only and simulated
*      supply current is 1/2 of total device current.
*
****************INPUT STAGE************** 
*
IOS 2 1 25.0P
*^Input offset current
CI1 1 0 3P
CI2 2 0 3P
R1 1 3 5E11
R2 3 2 5E11
I1 99 4 1.0M
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 650
R4 6 50 650
*Fp2=28 MHZ
C4 5 6 4.372P 
*
***********COMMON MODE EFFECT***********
*
I2 99 50 800UA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 1E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 20E-3
R5 98 9 10MEG
VA3 9 11 0
*Fp1=18 HZ
C3 98 11 857.516P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.305E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 144.7M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6  99 50 VA7 1
F5  99 23 VA8 1
D5  21 23 DX
VA7 99 21 0
D6  23 99 DX
E1  99 26 99 15 1
VA8 26 27 0
R16 27 28 50
V5  28 25 0.646V
D4  25 15 DX
V4  24 28 0.646V
D3  15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
*
.ENDS
*//////////////////////////////////////////////////////////
*LF451 Wide-Bandwidth JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:    non-inverting input
*                 |   inverting input
*                 |   |   positive power supply
*                 |   |   |   negative power supply
*                 |   |   |   |   output
*                 |   |   |   |   |
*                 |   |   |   |   |
.SUBCKT LF451     1   2  99  50  28
*
*Features:
*Low supply current =                3.4mA(max)
*Wide bandwidth =                     4MHz
*High slew rate =                   13V/uS
*Low offset voltage =                 10mV
*
****************INPUT STAGE************** 
*
IOS 2 1 25P
*^Input offset current
R1 1 3 5E11
R2 3 2 5E11
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=12 MHz
C4 5 6 3.31573E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 2.1MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 .3E-3 1
*Input offset voltage.^
R8 99 49 50K
R9 49 50 50K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA3 0 0 0 1.0985E7
G1 98 9 5 6 1E-3
R5 98 9 100MEG
VA3 9 11 0
*Fp1=40.3 HZ
C3 98 11 39.493P
*
***************POLE STAGE***************
*
*Fp3=42 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 3.7894E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 31.831M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6  99 50 VA7 1
F5  99 23 VA8 1
D5  21 23 DX
VA7 99 21 0
D6  23 99 DX
E1  99 26 99 15 1
VA8 26 27 0
R16 27 28 35
V5  28 25 0.1V
D4  25 15 DX
V4  24 28 0.1V
D3  15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12)
*
.ENDS
*//////////////////////////////////////////////////////////
*LF453 Wide-Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:    non-inverting input
*                 |   inverting input
*                 |   |   positive power supply
*                 |   |   |   negative power supply
*                 |   |   |   |   output
*                 |   |   |   |   |
*                 |   |   |   |   |
.SUBCKT LF453     1   2  99  50  28
*
*Features:
*Low supply current =                6.5mA(max)
*Wide bandwidth =                     4MHz
*High slew rate =                   13V/uS
*Low offset voltage =                  5mV(max)
*NOTE: Model is for single device only and simulated
*      supply current is 1/2 of total device current.
*
****************INPUT STAGE************** 
*
IOS 2 1 25P
*^Input offset current
R1 1 3 5E11
R2 3 2 5E11
I1 99 4 100U
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 20K
R4 6 50 20K
*Fp2=12 MHz
C4 5 6 3.31573E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 2.1MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 .3E-3 1
*Input offset voltage.^
R8 99 49 50K
R9 49 50 50K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA3 0 0 0 1.0985E7
G1 98 9 5 6 1E-3
R5 98 9 100MEG
VA3 9 11 0
*Fp1=40.3 HZ
C3 98 11 39.493P
*
***************POLE STAGE***************
*
*Fp3=42 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 3.7894E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 31.831M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6  99 50 VA7 1
F5  99 23 VA8 1
D5  21 23 DX
VA7 99 21 0
D6  23 99 DX
E1  99 26 99 15 1
VA8 26 27 0
R16 27 28 35
V5  28 25 0.1V
D4  25 15 DX
V4  24 28 0.1V
D3  15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12)
*
.ENDS
* COPYRIGHT OF NATIONAL SEMICONDUCTOR CORP.
*
* Library of National Semiconductor Corp. CMOS OP-AMP
* Macromodels.  Version 2.5
*
* This library of macromodels is being supplied to users as
* an aid to circuit designs.  While it reflects reasonably 
* close similarity to the actual device in terms of
* performance, it is not suggested as a replacement for
* breadboarding.  Simulation should be used as a supplement
* to traditional lab testing.
*
* Users should very carefully note the following factors
* regarding these models:
*
* -- Model performance in general will reflect typical
* baseline specs for a given device, and certain aspects of
* performance may not be modeled fully.
*
* -- While reasonable care has been taken in their
* preparation, we cannot be responsible for correct
* application on any and all computer systems.
*
* -- Model users are hereby notified that these models are
* supplied "as is", with no direct or implied responsibility
* on the part of National Semiconductor for their operation
* within a customer circuit or system.  Further, National
* Semiconductor reserves the right to change these models
* without prior notice.
*
* -- In all cases, the current data sheet information for a
* given real device is your final design guideline, and is
* the only actual performance guarantee.  For further
* technical information, refer to individual device data
* sheets.
*
* Note: The current models presently do not simulate
* temperature or noise effects. 
*
* Your feedback and suggestions on these (and future) models
* will be appreciated.
*
* Models developed by:
* David Hindi
* National Semiconductor       For information on the models, contact:
* 2900 Semiconductor Dr.       Linear Applications    
* Santa Clara, CA 95052        [phone] 
* M/S C2500                     
* FAX [phone]           For ordering information, contact:
*                              Customer Response Center
*                              [phone]
* ---------------------------------------------------------
*//////////////////////////////////////////////////////////
*LMC660AM/AI/C CMOS Quad OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:      non-inverting input
*                   |   inverting input
*                   |   |   positive power supply
*                   |   |   |   negative power supply
*                   |   |   |   |   output
*                   |   |   |   |   |
*                   |   |   |   |   |
.SUBCKT LMC660      1   2  99  50  41
*
*Features:
*Operates from single supply
*Rail-to-rail output swing
*Ultra low input current =             40fA
*Slew rate =                        1.1V/uS
*
*NOTE: Model is for single device only and simulated
*      supply current is 1/4 of total device current.
*      Noise is not modeled.
*      Asymmetrical gain is not modeled.
*
*****************INPUT STAGE************** 
*
I1  99  4 20U
M1   5  2 4 99 MOSFET
R3   5 50 5.2696K
M2   6  7 4 99 MOSFET
R4   6 50 5.2696K
*Fp2=7.5 MHz
C4   5  6 2.0135P
CI1  1  0 2P
CI2  2  0 2P
DP1  1 99 DA
DP2 50  1 DX
DP3  2 99 DX
DP4 50  2 DB
G0  98  9 6 5 23.721E-3
R0  98  9 1K
*For accurate Ib , set GMIN<=1E-16 on .OPTIONS line.
*
***********COMMON MODE EFFECT***********
*
I2  99 50 305U
*^Quiescent current                   
EOS  7  1 POLY(1) 16 49 1E-3 1
*Offset voltage.........^
R8  99 49 100K
R9  49 50 100K
*
***************POLE STAGE*************** 
*
*Fp=13.3 MHz
G3  98 15 9 49 1E-3
R12 98 15 1K
C5  98 15 11.967P
*
************POLE/ZERO STAGE*************
*
*Fp=1 MHz, Fz= 2.6MHz
G5  98 18 15 49 1E-3
R14 98 18 1K
R15 98 19 625
C6  19 18 97.94P
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=20 KHz
G4  98 16 POLY(2) 1 49 2 49 0 3.5397E-8 3.5397E-8
L2  98 17 7.958M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
EH  99 98 99 49 1
G1  98 29 18 49 8.253E-6
R5  98 29 510.8MEG
D1   8 99 DX
V2   8 29 1.363
D2  50 10 DX
V3  29 10 1.363
F6  99 50 VA7 1
*^Dynamic supply current
F5  99 35 VA8 1
D3  36 35 DX
VA7 99 36 0
D4  35 99 DX
E1  99 37 99 49 1
VA8 37 38 0
G6  38 40 49 29 11.765E-3
R16 38 40 2.688K  
D5  30 99 DX
V4  30 40 .77
D6  50 31 DX
V5  40 31 .77
*Fp1=.5294 Hz
C3  29 39 18.182P
R6  39 40 1K
R17 40 41 47
*
***************MODELS USED**************
*
.MODEL DA D(IS=5E-14)
.MODEL DB D(IS=4E-14)
.MODEL DX D(IS=1E-14)
.MODEL MOSFET PMOS(VTO=-2.35 KP=1.801E-3)
.ENDS
*//////////////////////////////////////////////////////////
*LPC660AM/AI/I CMOS Quad OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:      non-inverting input
*                   |   inverting input
*                   |   |   positive power supply
*                   |   |   |   negative power supply
*                   |   |   |   |   output
*                   |   |   |   |   |
*                   |   |   |   |   |
.SUBCKT LPC660      1   2  99  50  41
*
*Features:
*Operates from single supply
*Rail-to-rail output swing
*Ultra low input current =             40fA
*Slew rate =                        .11V/uS
*
*NOTE: Model is for single device only and simulated
*      supply current is 1/4 of total device current.
*      Noise is not modeled.
*      Asymmetrical gain is not modeled.
*
*****************INPUT STAGE************** 
*
I1  99  4 1U
M1   5  2 4 99 MOSFET
R3   5 50 37.65K
M2   6  7 4 99 MOSFET
R4   6 50 37.65K
*Fp2=345 KHz
C4   5  6 6.126P
CI1  1  0 2P
CI2  2  0 2P
DP1  1 99 DA
DP2 50  1 DX
DP3  2 99 DX
DP4 50  2 DB
G0  98  9 6 5 66.402E-3
R0  98  9 1K
*For accurate Ib , set GMIN<=1E-16 on .OPTIONS line.
*