acc.v

来自「MAX+PLUSII教材及实例-西文-152页-1.7M-PDF版.zip」· Verilog 代码 · 共 35 行

module acc (yn, xh, clk, first);

input [10:0] xh;
input clk, first;
output [11:4] yn;

wire [11:0] xh_int;
reg [11:0]  ynm;
reg [11:0] yn_int;

assign xh_int = {1'b0, xh[10:0]};

always @(first or yn)
begin
	if (!first)
		ynm = yn_int;
	else
		ynm = 12'b0;
end

always @(posedge clk)
	begin
		yn_int = xh_int + ynm;
	end

assign yn = yn_int[11:4];
 
endmodule