📄 devhelp.txt
字号:
Mnemonic: F253 Mnemonic: DIP
Pin Count: 20 Total Product Terms: 42
Extensions: OE
_____________________________________________________________
Manufacturer Device Name
------------ -----------
GOULD PEEL253
ICT PEEL253
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): 20 GND(s): 10
Input Only: 1 2 3 4 5 6 7 8
Output Only:
Input/Output: 9 11 12 13 14 15 16 17 18 19
%%
%F2552
F2552 Architecture
Mnemonic: F2552 Mnemonic: DIP
Pin Count: 68 Total Product Terms: 226
Extensions: D J K OE CK AP AR DQ
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PML2552
_____________________________________________________________
Clock Pin(s): 20 21 22 23 Common OE(s):
24 36 56 65
VCC(s): 4 27 38 55 GND(s): 15 32 49 66
Input Only: 8 9 10 11 12 13 14 16 17 20 21 22
23 24 26 28 29 30 31 33 34 35 37 39
40 41 42 43 44 45
Output Only:
Input/Output: 1 2 3 5 6 7 46 47 48 50 51 52 53
54 57 58 59 60 61 62 63 64 67 68
%%
%F273
F273 Architecture
Mnemonic: F273 Mnemonic: DIP
Pin Count: 24 Total Product Terms: 42
Extensions: OE
_____________________________________________________________
Manufacturer Device Name
------------ -----------
GOULD PEEL273
ICT PEEL273
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): 24 GND(s): 12
Input Only: 1 2 3 4 5 6 7 8 9 10 11 13
Output Only:
Input/Output: 14 15 16 17 18 19 20 21 22 23
%%
%F2852
F2852 Architecture
Mnemonic: F2852 Mnemonic: DIP
Pin Count: 84 Total Product Terms: 226
Extensions: D J K OE CK AP AR DQ
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PML2852
_____________________________________________________________
Clock Pin(s): 24 26 27 28 Common OE(s):
44 68 81
VCC(s): 4 25 33 46 67 GND(s): 19 40 61 82
Input Only: 12 13 14 15 16 17 18 20 21 24 26 27
28 30 31 32 34 35 36 37 38 39 41 42
43 45 47 48 49
Output Only: 8 9 10 11 50 51 52 53 54 55 56 57
71 72 73 74
Input/Output: 1 2 3 5 6 7 69 70 75 76 77 78 79
80 83 84
%%
%F30K12
F30K12 Architecture
Mnemonic: F30K12 Mnemonic: DIP
Pin Count: 28 Total Product Terms: 72
Extensions: S R CA OE AP AR OBS CKMUX
_____________________________________________________________
Manufacturer Device Name
------------ -----------
AMD/MMI PLS30K12
_____________________________________________________________
Clock Pin(s): 1 4 Common OE(s):
VCC(s): 28 GND(s): 14
Input Only: 2 3 4 5 6 7 21 22 23 24 25 26 27
Output Only: 8 9 10 11 12 13 15 16 17 18 19 20
Input/Output:
%%
%F30S16
F30S16 Architecture
Mnemonic: F30S16 Mnemonic: DIP
Pin Count: 28 Total Product Terms: 71
Extensions: S R CA OE AP AR OBS DQ CKMUX
_____________________________________________________________
Manufacturer Device Name
------------ -----------
AMD/MMI PLS30S16
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F405
F405 Architecture
Mnemonic: F405 Mnemonic: DIP
Pin Count: 28 Total Product Terms: 64
Extensions: J K S R CA OE AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PLUS405
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F415
F415 Architecture
Mnemonic: F415 Mnemonic: DIP
Pin Count: 28 Total Product Terms: 68
Extensions: J K CA OE AP AR CKMUX OEMUX APMUX ARMUX
_____________________________________________________________
Manufacturer Device Name
------------ -----------
ATMEL ATS415
PHILIPS PLC415
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F42VA12
F42VA12 Architecture
Mnemonic: F42VA12 Mnemonic: DIP
Pin Count: 24 Total Product Terms: 105
Extensions: OE D AR AP J K CA OEMUX CK IO
_____________________________________________________________
Manufacturer Device Name
------------ -----------
ATMEL ATS42VA12
PHILIPS PLC42VA12
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F42VA12lcc
F42VA12lcc Architecture
Mnemonic: F42VA12lcc Mnemonic: PLCC
Pin Count: 28 Total Product Terms: 105
Extensions: OE D AR AP J K CA OEMUX CK IO
_____________________________________________________________
Manufacturer Device Name
------------ -----------
ATMEL ATS42VA12
PHILIPS PLC42VA12
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F473
F473 Architecture
Mnemonic: F473 Mnemonic: DIP
Pin Count: 24 Total Product Terms: 24
Extensions: OE
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PLC473
PHILIPS PLHS473
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F473lcc
F473lcc Architecture
Mnemonic: F473lcc Mnemonic: PLCC
Pin Count: 28 Total Product Terms: 24
Extensions: OE
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PLC473
PHILIPS PLHS473
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F48N22
F48N22 Architecture
Mnemonic: F48N22 Mnemonic: DIP
Pin Count: 68 Total Product Terms: 73
Extensions: OE
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PHD48N22
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F501
F501 Architecture
Mnemonic: F501 Mnemonic: DIP
Pin Count: 52 Total Product Terms: 112
Extensions: OE CA
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PLHS501
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1. The F501 contains a NAND array architecture. The NAND
gates must be defined as complement array nodes.
2. Although there is only one product term for each output
pin, multiple product term output can be implemented
using DeMorgan's algorithm and NAND nodes.
For example, to implement the following logical
function:
X = (a & b)
# (c & d)
# (e & f);
Define as follows:
Pin 19 = X;
Pinnode 53 = !X1;
Pinnode 54 = !X2;
Pinnode 55 = !X3;
X = !(!X1 & !X2 & !X3);
X1.ca = a & b;
X2.ca = c & d;
X3.ca = e & f;
%%
%F502
F502 Architecture
Mnemonic: F502 Mnemonic: DIP
Pin Count: 64 Total Product Terms: 144
Extensions: OE CA D S R AR CK
_____________________________________________________________
Manufacturer Device Name
------------ -----------
PHILIPS PLHS502
_____________________________________________________________
Clock Pin(s): Common OE(s):
VCC(s): GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1. The F502 contains a NAND array architecture. The NAND
gates must be defined as complement array nodes.
2. Although there is only one product term for each output
pin, multiple product term output can be implemented
using DeMorgan's algorithm and NAND nodes.
For example, to implement the following logical
function:
X = (a & b)
# (c & d)
# (e & f);
Define as follows:
Pin 19 = X;
Pinnode 81 = !X1;
Pinnode 82 = !X2;
Pinnode 83 = !X3;
X = !(!X1 & !X2 & !X3);
X1.ca = a & b;
X2.ca = c & d;
X3.ca = e & f;
%%
%F506
F506 Architecture
Mnemonic: F506 Mnemonic: DIP
Pin Count: 24 Total Product Terms: 98
Extensions: S R CA OE CKMUX
_____________________________________________________________
Manufacturer Device Name
------------ -----------
TI TIBPLS506A
_____________________________________________________________
Clock Pin(s): 1 Common OE(s): 17
VCC(s): 24 GND(s): 12
Input Only: 2 3 4 5 6 7 17 18 19 20 21 22 23
Output Only: 8 9 10 11 13 14 15 16
Input/Output:
_____________________________________________________________
Device Notes:
1. The registered clock polarity is set by writing one
.CKMUX expression for all registers used in the design.
By default, the clock is treated as positive-edge
triggered.
2. Pin 17 (dip, 20 lcc) can be programmed to function
as input only or input and output enable. The
following examples show how to do this:
Input only Input/Output enable
哪哪哪哪哪 哪哪哪哪哪哪哪哪哪⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -