devhelp.txt

Protel99-SE-软件.zip

Output Only:
Input/Output: 2  3  4  5  6  7  8  9  10  11  12  13  23
              24  25  26  27  28  29  30  31  32  33  34
              36  37  38  39  40  41  42  43  44  45  46
              47  50  57  58  59  60  61  62  63  64  65
              66  67  68
_____________________________________________________________
Device Notes:
1.  Miser bits:    42480-42487
    Turbo bits:    42488-42489
%%
%EP300
EP300 Architecture
Mnemonic: EP300               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   74
Extensions: OE D AR SP INT DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP300
ALTERA                        EP310
INTEL                         5C031
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.   The registered, internal combinatorial and I/O feedback
     paths can be selected by using the .DFB, .INT and .IO
     extensions respectively. If the feedback type is the
     same as the output (registered feedback for registered
     output), a feedback extension is not required.
%%
%EP312
EP312 Architecture
Mnemonic: EP312               Mnemonic: DIP
Pin Count: 24             Total Product Terms:  200
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP512
INTEL                         5AC312
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Latch Enable: 13
Input Only: 1  3  4  5  6  7  8  9  10  13
Output Only:
Input/Output: 2  11  14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  Turbo bit:     13712
%%
%EP312lcc
EP312lcc Architecture
Mnemonic: EP312               Mnemonic: PLCC
Pin Count: 24             Total Product Terms:  200
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP512
INTEL                         5AC312
_____________________________________________________________
Clock Pin(s): 2               Common OE(s):
VCC(s): 1  28                 GND(s): 14  15
Latch Enable: 16
N/C:  11  19
Input Only: 2  4  5  6  7  8  9  10  16
Output Only:
Input/Output: 3  13  17  18  20  21  22  23  24  25  26  27
_____________________________________________________________
Device Notes:
1.  Turbo bit:     13712
%%
%EP320
EP320 Architecture
Mnemonic: EP320               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP320
ALTERA                        EP330
INTEL                         5C032
INTEL                         85C220
TI                            EP330
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.  Miser bits:    2912-2913
    Turbo bits:    2914-2915
%%
%EP324
EP324 Architecture
Mnemonic: EP324               Mnemonic: DIP
Pin Count: 40             Total Product Terms:  394
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         5AC324
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 13  33                GND(s): 8  28
Latch Enable: 21
Input Only: 1  2  3  18  19  20  21  22  23  38  39  40
Output Only:
Input/Output: 4  5  6  7  9  10  11  12  14  15  16  17  24
               25  26  27  29  30  31  32  34  35  36  37
_____________________________________________________________
Device Notes:
1.  Turbo bit:     47492
%%
%EP324lcc
EP324lcc Architecture
Mnemonic: EP324lcc            Mnemonic: PLCC
Pin Count: 40             Total Product Terms:  394
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         5AC324
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Latch Enable:
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  Turbo bit:     47492
%%
%EP600
EP600 Architecture
Mnemonic: EP600               Mnemonic: DIP
Pin Count: 24             Total Product Terms:  160
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP600
ALTERA                        EP610
ALTERA                        EP610T
ALTERA                        EP630
AMD/MMI                       PALCE610
CYPRESS                       CY7B326
INTEL                         5C060
INTEL                         85C060
TI                            EP610
TI                            EP630
_____________________________________________________________
Clock Pin(s): 1  13           Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 2  11  14  23
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19
              20  21  22
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    6480-6481
     EP900/910 Turbo bits:    17400-17401
%%
%EP600lcc
EP600lcc Architecture
Mnemonic: EP600lcc        Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  160
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP600
ALTERA                        EP610
ALTERA                        EP610T
ALTERA                        EP630
AMD/MMI                       PALCE610
CYPRESS                       CY7B326
INTEL                         5C060
INTEL                         85C060
TI                            EP610
TI                            EP630
_____________________________________________________________
Clock Pin(s): 2  16           Common OE(s):
VCC(s): 1  28                 GND(s): 14  15
Input Only: 2  3  13  16  17  27
Output Only:
Input/Output: 4  5  6  7  8  9  10  12  18  20  21  22  23
              24  25  26
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    6480-6481
     EP900/910 Turbo bits:    17400-17401
%%
%EP900
EP900 Architecture
Mnemonic: EP900               Mnemonic: DIP
Pin Count: 40             Total Product Terms:  240
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP900
ALTERA                        EP910
ALTERA                        EP910A
ALTERA                        EP910T
INTEL                         5C090
INTEL                         85C090
TI                            EP910
_____________________________________________________________
Clock Pin(s): 1  21           Common OE(s):
VCC(s): 40                    GND(s): 20
Input Only: 2  3  4  17  18  19  22  23  24  37  38  39
Output Only:
Input/Output: 5  6  7  8  9  10  11  12  13  14  15  16  25
               26  27  28  29  30  31  32  33  34  35  36
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    17400-17401
%%
%EP900lcc
EP900lcc Architecture
Mnemonic: EP900lcc        Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  240
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP900
ALTERA                        EP910
ALTERA                        EP910A
ALTERA                        EP910T
INTEL                         5C090
INTEL                         85C090
TI                            EP910
_____________________________________________________________
Clock Pin(s): 2  24           Common OE(s):
VCC(s): 1  44                 GND(s): 22  23
N/C:  17  29
Input Only: 3  4  5  19  20  21  25  26  27  41  42  43
Output Only:
Input/Output: 6  7  8  9  10  11  12  13  14  15  16  18  28
               29  30  31  32  33  34  35  36  37  38  40
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    17400-17401
%%
%F100
F100 Architecture
Mnemonic: F100                Mnemonic: DIP
Pin Count: 28             Total Product Terms:   48
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     93Z458
FAIRCHILD                     93Z459
PHILIPS                       82S100
PHILIPS                       82S101
PHILIPS                       PLS100
PHILIPS                       PLS101
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 19
VCC(s): 28                    GND(s): 14
Input Only: 2  3  4  5  6  7  8  9  20  21  22  23  24  25
            26  27

Output Only: 10  11  12  13  15  16  17  18
Input/Output:
Unused: 1
%%
%F103
F103 Architecture
Mnemonic: F103                Mnemonic: DIP
Pin Count: 28             Total Product Terms:    9
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S103
PHILIPS                       PLS103
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):