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📁 Protel99-SE-软件.zip
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 CEO = CE & TC;
 [Q0, Q1].ar = CLR;
 TC = Q0 & Q1;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 [Q0, Q1].ck = C;
 [Q0, Q1].ce = CE;
 CEO = CE & TC;
 [Q0, Q1].ar = CLR;
 TC = Q0 & Q1;
END
BODY-UNCONNECTED
 CE = 'b'1;
 CLR = 'b'0;
 L = 'b'0;
 D0 = 'b'0;
 D1 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  2-Bit Loadable Cascadable Bidirectional Binary
--  Counter with Clock Enable and Asynchronous Clear
----------------------------------
SYMBOL (CB2CLED,11)
PINS
[D0-HI] [D1-HI] [L-HI] [UP-HI] [CE-HI] [C-HI] [CLR-HI]
[Q0-POH] [Q1-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q1, Q0] = 1;
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L & CE
      # !Q0 &!UP & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 CEO = CE & TC;
 [Q0, Q1].ar = CLR;
 TC = Q0 & Q1 & UP
    #!Q0 &!Q1 &!UP & !CLR;
END
BODY-CPLD
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L & CE
      # !Q0 &!UP & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 [Q0, Q1].ck = C;
 CEO = CE & TC;
 [Q0, Q1].ar = CLR;
 TC = Q0 & Q1 & UP
    #!Q0 &!Q1 &!UP & !CLR;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L
      # !Q0 &!UP & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 [Q0, Q1].ck = C;
 [Q0, Q1].ce = CE;
 CEO = CE & TC;
 [Q0, Q1].ar = CLR;
 TC = Q0 & Q1 & UP
    #!Q0 &!Q1 &!UP & !CLR;
END
BODY-UNCONNECTED
 CE = 'b'1;
 CLR = 'b'0;
 L = 'b'0;
 UP = 'b'1;
 D0 = 'b'0;
 D1 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  2-Bit Cascadable Binary Counter with
--  Clock Enable and Synchronous Clear
----------------------------------
SYMBOL (CB2RE,7)
PINS
[CE-HI] [C-HI] [R-HI] [Q0-POH] [Q1-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
-- We need to do something about the Reset Term for Simple Devices without Synchronous Reset
 REGISTER_SELECT [Q1, Q0] = 1;
 Q0.t = 'b'1 & CE & !R
      # R & Q0;
 Q1.t = Q0 & CE & !R
      # R & Q1;
 CEO = CE & TC;
 TC = Q0 & Q1;
END
BODY-CPLD
 Q0.t = 'b'1 & CE;
 Q1.t = Q0 & CE;
 [Q0, Q1].ck = C;
 CEO = CE & TC;
 [Q0, Q1].sr = R;
 TC = Q0 & Q1;
END
BODY-FPGA
 Q0.t = 'b'1;
 Q1.t = Q0;
 [Q0, Q1].ck = C;
 [Q0, Q1].ce = CE;
 CEO = CE & TC;
 [Q0, Q1].sr = R;
 TC = Q0 & Q1;
END
BODY-UNCONNECTED
 CE = 'b'1;
 R = 'b'0;
END
%%
----------------------------------

----------------------------------
--  2-Bit Loadable Cascadable Binary Counter with
--  Clock Enable and Synchronous Clear
----------------------------------
SYMBOL (CB2RLE,10)
PINS
[D0-HI] [D1-HI] [L-HI] [CE-HI] [C-HI] [R-HI]
[Q0-POH] [Q1-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q1, Q0] = 1;
 Q0.t = 'b'1 & !L & CE & !R
      #   Q0 & R
      #  !Q0 &  L &  D0 & !R
      #   Q0 &  L & !D0 & !R;
 Q1.t = Q0 & !L & CE & !R
      # Q1 & RST
      # !Q1 & L &  D1 & !R
      #  Q1 & L & !D1 & !R;
 CEO = CE & TC;
 TC = Q0 & Q1;
END
BODY-CPLD
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 [Q0, Q1].ck = C;
 CEO = CE & TC;
 [Q0, Q1].sr = R;
 TC = Q0 & Q1;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 [Q0, Q1].ck = C;
 [Q0, Q1].ce = CE;
 CEO = CE & TC;
 [Q0, Q1].sr = R;
 TC = Q0 & Q1;
END
BODY-UNCONNECTED
 CE = 'b'1;
 R = 'b'0;
 L = 'b'0;
 D0 = 'b'0;
 D1 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  4-Bit Cascadable Binary Counter with
--  Clock Enable and Asynchronous Clear
----------------------------------
SYMBOL (CB4CE,9)
PINS
[CE-HI] [C-HI] [CLR-HI]
[Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & CE;
 Q1.t = Q0 & CE;
 Q2.t = Q0 & Q1 & CE;
 Q3.t = Q0 & Q1 & Q2 & CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-CPLD
 Q0.t = 'b'1 & CE;
 Q1.t = Q0 & CE;
 Q2.t = Q0 & Q1 & CE;
 Q3.t = Q0 & Q1 & Q2 & CE;
 [Q0, Q1, Q2, Q3].ck = C;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-FPGA
 Q0.t = 'b'1;
 Q1.t = Q0;
 Q2.t = Q0 & Q1;
 Q3.t = Q0 & Q1 & Q2;
 [Q0, Q1, Q2, Q3].ck = C;
 [Q0, Q1, Q2, Q3].ce = CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-UNCONNECTED
 CE = 'b'1;
 CLR = 'b'0;
END
%%
----------------------------------

----------------------------------
--  4-Bit Loadable Cascadable Binary Counter with
--  Clock Enable and Asynchronous Clear
----------------------------------
SYMBOL (CB4CLE,14)
PINS
[D0-HI] [D1-HI] [D2-HI] [D3-HI] [L-HI] [CE-HI] [C-HI] [CLR-HI]
[Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t = Q0 & Q1 & !L & CE
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t = Q0 & Q1 & Q2 & !L & CE
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-CPLD
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t = Q0 & Q1 & !L & CE
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t = Q0 & Q1 & Q2 & !L & CE
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t = Q0 & Q1 & !L
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t = Q0 & Q1 & Q2 & !L
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 [Q0, Q1, Q2, Q3].ce = CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-UNCONNECTED
 CE = 'b'1;
 CLR = 'b'0;
 L = 'b'0;
 D0 = 'b'0;
 D1 = 'b'0;
 D2 = 'b'0;
 D3 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  4-Bit Loadable Cascadable Bidirectional Binary
--  Counter with Clock Enable and Asynchronous Clear
----------------------------------
SYMBOL (CB4CLED,15)
PINS
[D0-HI] [D1-HI] [D2-HI] [D3-HI] [L-HI] [UP-HI] [CE-HI] [C-HI] [CLR-HI]
[Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L & CE
      # !Q0 &!UP & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t =  Q0 & Q1 & UP & !L & CE
      # !Q0 &!Q1 &!UP & !L & CE
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t =  Q0 & Q1 & Q2 & UP & !L & CE
      # !Q0 &!Q1 &!Q2 &!UP & !L & CE
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3 & UP
    #!Q0 &!Q1 &!Q2 &!Q3 &!UP & !CLR;
END
BODY-CPLD
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L & CE
      # !Q0 &!UP & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t =  Q0 & Q1 & UP & !L & CE
      # !Q0 &!Q1 &!UP & !L & CE
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t =  Q0 & Q1 & Q2 & UP & !L & CE
      # !Q0 &!Q1 &!Q2 &!UP & !L & CE
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3 & UP
    #!Q0 &!Q1 &!Q2 &!Q3 &!UP & !CLR;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t =  Q0 & UP & !L
      # !Q0 &!UP & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t =  Q0 & Q1 & UP & !L
      # !Q0 &!Q1 &!UP & !L
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t =  Q0 & Q1 & Q2 & UP & !L
      # !Q0 &!Q1 &!Q2 &!UP & !L
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 [Q0, Q1, Q2, Q3].ce = CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].ar = CLR;
 TC = Q0 & Q1 & Q2 & Q3 & UP
    #!Q0 &!Q1 &!Q2 &!Q3 &!UP & !CLR;
END
BODY-UNCONNECTED
 CE = 'b'1;
 CLR = 'b'0;
 L = 'b'0;
 UP = 'b'1;
 D0 = 'b'0;
 D1 = 'b'0;
 D2 = 'b'0;
 D3 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  4-Bit Cascadable Binary Counter with
--  Clock Enable and Synchronous Clear
----------------------------------
SYMBOL (CB4RE,9)
PINS
[CE-HI] [C-HI] [R-HI] [Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & CE & !R
      #  Q0 & R;
 Q1.t = Q0 & CE & !R
      #  Q1 & R;
 Q2.t = Q0 & Q1 & CE & !R
      #  Q2 & R;
 Q3.t = Q0 & Q1 & Q2 & CE & !R
      #  Q3 & R;
 CEO = CE & TC;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-CPLD
 Q0.t = 'b'1 & CE;
 Q1.t = Q0 & CE;
 Q2.t = Q0 & Q1 & CE;
 Q3.t = Q0 & Q1 & Q2 & CE;
 [Q0, Q1, Q2, Q3].ck = C;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].sr = R;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-FPGA
 Q0.t = 'b'1;
 Q1.t = Q0;
 Q2.t = Q0 & Q1;
 Q3.t = Q0 & Q1 & Q2;
 [Q0, Q1, Q2, Q3].ck = C;
 [Q0, Q1, Q2, Q3].ce = CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].sr = R;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-UNCONNECTED
 CE = 'b'1;
 R = 'b'0;
END
%%
----------------------------------

----------------------------------
--  4-Bit Loadable Cascadable Binary Counter with
--  Clock Enable and Synchronous Clear
----------------------------------
SYMBOL (CB4RLE,14)
PINS
[D0-HI] [D1-HI] [L-HI] [CE-HI] [C-HI] [R-HI]
[Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & !L & CE & !R
      #  !Q0 &  L &  D0 & !R
      #   Q0 &  L & !D0 & !R
      #   Q0 & R;
 Q1.t = Q0 & !L & CE & !R
      # !Q1 & L &  D1 & !R
      #  Q1 & L & !D1 & !R
      #  Q1 & R;
 Q2.t = Q0 & Q1 & !L & CE & !R
      # !Q2 & L &  D2 & !R
      #  Q2 & L & !D2 & !R
      #  Q2 & R;
 Q3.t = Q0 & Q1 & Q2 & !L & CE & !R
      # !Q3 & L &  D3 & !R
      #  Q3 & L & !D3 & !R
      #  Q3 & R;
 CEO = CE & TC;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-CPLD
 Q0.t = 'b'1 & !L & CE
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L & CE
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t = Q0 & Q1 & !L & CE
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t = Q0 & Q1 & Q2 & !L & CE
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].sr = R;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-FPGA
 Q0.t = 'b'1 & !L
      #  !Q0 &  L &  D0
      #   Q0 &  L & !D0;
 Q1.t = Q0 & !L
      # !Q1 & L &  D1
      #  Q1 & L & !D1;
 Q2.t = Q0 & Q1 & !L
      # !Q2 & L &  D2
      #  Q2 & L & !D2;
 Q3.t = Q0 & Q1 & Q2 & !L
      # !Q3 & L &  D3
      #  Q3 & L & !D3;
 [Q0, Q1, Q2, Q3].ck = C;
 [Q0, Q1, Q2, Q3].ce = CE;
 CEO = CE & TC;
 [Q0, Q1, Q2, Q3].sr = R;
 TC = Q0 & Q1 & Q2 & Q3;
END
BODY-UNCONNECTED
 CE = 'b'1;
 R = 'b'0;
 L = 'b'0;
 D0 = 'b'0;
 D1 = 'b'0;
 D2 = 'b'0;
 D3 = 'b'0;
END
%%
----------------------------------

----------------------------------
--  8-Bit Cascadable Binary Counter with
--  Clock Enable and Asynchronous Clear
----------------------------------
SYMBOL (CB8CE,13)
PINS
[CE-HI] [C-HI] [CLR-HI]
[Q0-POH] [Q1-POH] [Q2-POH] [Q3-POH] [Q4-POH] [Q5-POH] [Q6-POH] [Q7-POH]
[CEO-IMH] [TC-IMH];
BODY-SPLD
 REGISTER_SELECT [Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0] = 1;
 Q0.t = 'b'1 & CE;
 Q1.t = Q0 & CE;
 Q2.t = Q0 & Q1 & CE;
 Q3.t = Q0 & Q1 & Q2 & CE;
 Q4.t = Q0 & Q1 & Q2 & Q3 & CE;
 Q5.t = Q0 & Q1 & Q2 & Q3 & Q4 & CE;
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