c37x.fit

Protel99-SE-软件.zip

" Device definition File (V3.10)
" -----------------------------
$ C371 2
$ CY7C371 2
" ---------------------------------------------------------------------------
" NODE definition
"  45 .. 116		Interconnect NODES
" 117 .. 148		Steering fuses on PTMs
" 149 .. 308            Product Terms on PTMs
" 309,310               Clock Polarity Fuses LAB1
" 311 .. 316            Special PTs (LAB 1 Global OE & AR/AP)
" 317,318               Clock Polarity Fuses LAB2
" 319 .. 324            Special PTs (LAB 2 Global OE & AR/AP)
" 325 .. 330            Double Registered Inputs
" ---------------------------------------------------------------------------
" ! ShowDbgFAILPARTITION ;
" ! ShowDbgPTALLOC ;
" ! ShowDbgBANKS ;
" ! ShowDbgROUTE ;
! LOGICPT 330
	-1 16 16 16 16 16 16 16 16 0 0 -1 0 16 16 16 16 16 16 16 16 -1
	-1 16 16 16 16 16 16 16 16 0 0 -1 0 16 16 16 16 16 16 16 16 -1
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
		0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
		0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
        0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
		0 0 1 1 1 1 1 1
        0 0 1 1 1 1 1 1
        1 1 1 1 1 1 ;

# ROUTE_MATRIX ;
"node numbers entering route matrix, minus numbers represent internal feedback
! PIM_INPUTS 70
  -2 -21  -3 -20  -4 -19  -5 -18  -6 -17  -7 -16  10  -8 -15  -9 -14
  21   2  20   3  11  19   4  18   5  17   6  16   7  13  15   8  14   9
  36  31  37  30  32  38  29  39  28  40  27  41  26  33  42  25  43  24
 -31 -36 -30 -37  35 -29 -38 -28 -39 -27 -40 -26 -41 -25 -42 -24 -43 ;
" node numbers exiting route matrix
! PIM_OUTPUTS 45..116 ;
" ---------------------------------------------------------------------------
# PT_ALLOCATE
! PT_ARRAY 0
		16    0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15   ;
        16    0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0   ;
        16    0  0  0  0  0  0  1  1  1  1  2  2  2  2  3  3   ;
! PT_ARRAY 1
		16    6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21   ;
        16    1  1  1  1  1  1  1  1  1  1  0  0  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 2
		16   10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25   ;
        16    2  2  2  2  2  2  1  1  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 3
		16   14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29   ;
        16    3  3  2  2  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 4
		16   18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 5
		16   22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 6
		16   26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 7
		16   30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 8
		16   34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 9
		16   38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 10
		16   42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 11
		16   46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  2  2  2  2  3  3  3  3   ;
! PT_ARRAY 12
		16   50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
		16    0  0  0  0  1  1  1  1  2  2  2  2  2  2  3  3   ;
! PT_ARRAY 13
		16   54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  1  1  1  1  1  1  2  2  2  2  2  2   ;
! PT_ARRAY 14
		16   58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73   ;
        16    3  3  3  3  2  2  2  2  1  1  1  1  0  0  0  0   ;
        16    0  0  0  0  0  0  1  1  1  1  1  1  1  1  1  1   ;
! PT_ARRAY 15
		16   64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79   ;
        16    3  3  2  2  2  2  1  1  1  1  0  0  0  0  0  0   ;
        16    0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0   ;
" ---------------------------------------------------------------------------
# LAB 1          ;
! IO_MC#      16 ;
! BURIED_MC#   0 ;
! PIM_IN_SRC#  8 ;
! INP_TO_LAB# 36 ;
! BANK_AP#     1 314 ;
! BANK_AR#     2 313 ;
! BANK_OE#     2   5  6 ;
! CLOCKS#      2  13 35 ;
" each entry is indexed to PIM_INPUTS
! MUX_INTERCONNECT
  ->   4   45  54  71  72
  ->   4   46  55  70  73
  ->   4   47  56  69  74
  ->   4   48  57  68  75
  ->   5   49  58  67  78  80
  ->   5   50  59  63  66  76
  ->   5   51  53  60  65  79
  ->   5   52  61  62  64  77
  ->   4   45  62  70  77
  ->   4   46  54  69  80
  ->   4   47  55  68  76
  ->   4   48  56  67  79
  ->   4   49  57  66  72
  ->   4   50  58  65  73
  ->   4   51  59  64  78
  ->   4   52  60  63  75
  ->   4   53  61  71  74

  ->   4   45  61  69  78
  ->   4   46  62  68  79
  ->   4   47  54  67  74
  ->   4   48  55  66  80
  ->   4   49  56  65  76
  ->   4   50  57  64  75
  ->   4   51  58  63  77
  ->   4   52  59  71  73
  ->   4   53  60  70  72
  ->   4   45  60  68  77
  ->   4   46  61  67  78
  ->   4   47  62  66  76
  ->   4   48  54  65  79
  ->   4   49  55  64  72
  ->   4   50  56  63  80
  ->   4   51  57  71  74
  ->   4   52  58  70  75
  ->   4   53  59  69  73

  ->   4   45  59  67  74
  ->   4   46  60  66  73
  ->   4   47  61  65  77
  ->   4   48  62  64  78
  ->   4   49  54  63  75
  ->   4   50  55  71  79
  ->   4   51  56  70  72
  ->   4   52  57  69  80
  ->   4   53  58  68  76
  ->   4   45  58  66  80
  ->   4   46  59  65  76
  ->   4   47  60  64  78
  ->   4   48  61  63  77
  ->   4   49  62  71  79
  ->   4   50  54  70  73
  ->   4   51  55  69  74
  ->   4   52  56  68  75
  ->   4   53  57  67  72

  ->   4   45  57  65  72
  ->   4   46  58  64  75
  ->   4   47  59  63  74
  ->   4   48  60  71  76
  ->   4   49  61  70  78
  ->   4   50  62  69  77
  ->   4   51  54  68  80
  ->   4   52  55  67  79
  ->   4   53  56  66  73
  ->   5   45  55  56  64  78
  ->   5   46  53  57  63  77
  ->   4   47  58  71  79
  ->   4   48  59  70  75
  ->   4   49  60  69  80
  ->   5   50  61  68  73  76
  ->   4   51  62  67  72
  ->   5   52  54  66  65  74 ;
"list of interconnect inputs into LAB
! PIM# 36
         45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60
         61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76
		 77  78  79  80 ;
"Block A signals ordered 1->  N crossref'd against total device signals
! PINXREF 52
         45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60
		 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76
         77  78  79  80
         21  20  19  18  17  16  15  14   9   8   7   6   5   4   3   2 ;
"Macrocell types used by Utilization tables
! CELL     P P P P P P P P P P P P P P P P P P
           P P P P P P P P P P P P P P P P P P
           B B B B B B B B B B B B B B B B ;
"Block A macrocell physical assignment
! MCELLPOS 16	2  3  4  5  6  7  8  9 14 15 16 17 18 19 20 21 ;
"Block A I/O macrocells supporting dual feedback
! FB2_IO 16 21  20  19  18  17  16  15  14   9   8   7   6   5   4   3   2 ;
"Block A pinout diagram
! PINOUT 144
    0  45   0   0       0  46   0   2      0  47   0   0      0  48   0   3
    0  49   0   0       0  50   0   4      0  51   0   0      0  52   0   5
    0  53   0   0       0  54   0   6      0  55   0   0      0  56   0   7
	0  57   0   0       0  58   0   8      0  59   0   0      0  60   0   9
    0  61   0   0       0  62   0  14      0  63   0   0      0  64   0  15
    0  65   0   0       0  66   0  16      0  67   0   0      0  68   0  17
    0  69   0   0       0  70   0  18      0  71   0   0      0  72   0  19
	0  73   0   0       0  74   0  20      0  75   0   0      0  76   0  21
    0  77   0   0       0  78   0   0      0  79   0   0      0  80   0   0 ;

"Block A product term input signal order
! PT 72
      45  -45   46  -46   47  -47   48  -48   49  -49   50  -50   51  -51
      52  -52   53  -53   54  -54   55  -55   56  -56   57  -57   58  -58
      59  -59   60  -60   61  -61   62  -62   63  -63   64  -64   65  -65
	  66  -66   67  -67   68  -68   69  -69   70  -70   71  -71   72  -72
      73  -73   74  -74   75  -75   76  -76   77  -77   78  -78   79  -79
      80  -80 ;
" ---------------------------------------------------------------------------
# LAB 2          ;
! IO_MC#      16 ;
! BURIED_MC#   0 ;
! PIM_IN_SRC#  8 ;
! INP_TO_LAB# 36 ;
! BANK_AP#     3 322 ;
! BANK_AR#     4 321 ;
! BANK_OE#     2   9 10 ;
! CLOCKS#      2  13 35 ;
! MUX_INTERCONNECT
  ->   4   81  90 107 108
  ->   4   82  91 106 109
  ->   4   83  92 105 110
  ->   4   84  93 104 111
  ->   5   85  94 103 114 116
  ->   5   86  95  99 102 112
  ->   5   87  89  96 101 115
  ->   5   88  97  98 100 113
  ->   4   81  98 106 113
  ->   4   82  90 105 116
  ->   4   83  91 104 112
  ->   4   84  92 103 115
  ->   4   85  93 102 108
  ->   4   86  94 101 109
  ->   4   87  95 100 114
  ->   4   88  96  99 111
  ->   4   89  97 107 110

  ->   4   81  97 105 114
  ->   4   82  98 104 115
  ->   4   83  90 103 110
  ->   4   84  91 102 116
  ->   4   85  92 101 112
  ->   4   86  93 100 111
  ->   4   87  94  99 113
  ->   4   88  95 107 109
  ->   4   89  96 106 108
  ->   4   81  96 104 113
  ->   4   82  97 103 114
  ->   4   83  98 102 112
  ->   4   84  90 101 115
  ->   4   85  91 100 108
  ->   4   86  92  99 116
  ->   4   87  93 107 110
  ->   4   88  94 106 111
  ->   4   89  95 105 109

  ->   4   81  95 103 110
  ->   4   82  96 102 109
  ->   4   83  97 101 113
  ->   4   84  98 100 114
  ->   4   85  90  99 111
  ->   4   86  91 107 115
  ->   4   87  92 106 108
  ->   4   88  93 105 116
  ->   4   89  94 104 112
  ->   4   81  94 102 116
  ->   4   82  95 101 112
  ->   4   83  96 100 114
  ->   4   84  97  99 113
  ->   4   85  98 107 115
  ->   4   86  90 106 109
  ->   4   87  91 105 110
  ->   4   88  92 104 111
  ->   4   89  93 103 108

  ->   4   81  93 101 108
  ->   4   82  94 100 111
  ->   4   83  95  99 110
  ->   4   84  96 107 112
  ->   4   85  97 106 114
  ->   4   86  98 105 113
  ->   4   87  90 104 116
  ->   4   88  91 103 115
  ->   4   89  92 102 109
  ->   5   81  91  92 100 114
  ->   5   82  89  93  99 113
  ->   4   83  94 107 115
  ->   4   84  95 106 111
  ->   4   85  96 105 116
  ->   5   86  97 104 109 112
  ->   4   87  98 103 108
  ->   5   88  90 102 101 110 ;
"list of interconnect inputs into LAB
! PIM# 36
         81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96
         97  98  99 100 101 102 103 104 105 106 107 108 109 110 111 112
        113 114 115 116 ;