powerup_adcs&dacs.asm

电子元件资料大全-170M-pdf.zip

/**********************************************************************************
 *                     AKM ADC/DAC Reset and Configuration                        *
 *                                                                                *
 *  This routine resets and enables the AKM Semiconductor ADCs and DACs for       *
 *  96 KHz operation.                                                             *
 *                                                                                *
 *  J.T.                                                                          *
 *  Analog Devices, Inc.                                                          *
 *  DSP Applications Group                                                        *
 *  Rev 1.0                                                                       *
 *  2/1/99                                                                        *
 **********************************************************************************/

.GLOBAL Enable_AKM_Converters;

#include "def21065L.h"
#include "new65Ldefs.h"

#define		ADDA_CONFIG_REG	0x3000030

#define		ADHPFE		0x80
#define		DADEM1		0x40
#define		DADEM0		0x20
#define		DFS			0x10
#define		DAMUTE		0x08
#define		ANRST		0x04
#define		RES_BIT0	0x02
#define		RES_BIT1	0x01

/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 
	AD/DA Register Bit Settings
	-----------------------------
	Bit #   Symbol     	Function
	------- ---------   ---------
	D7 	   	AD_HPFE	  	=1, Enable the A/D converter's high pass filter
	D6		DA_DEM1		Bit 1, AK4394 DAC de-emphasis filters
	D5		DA_DEM0		Bit 0, AK4324 DAC de-emphasis filters
	D4		DFS			=1 96 KHz Operation, =0 48 KHz operation
	D3		DA_MUTE		=1 to mute the D/A converters, =0 to enable outputs
	D2		ANRST		=0 to reset A/Ds and D/As, =1 normal operating mode
	D1		RES			Reserved for future expansion
	D0		RES			Reserved for future expansion 

	Sample Rate Modes (DA-De-Emphasis bit Settings)
	-----------------------------------------------
    BIT #:	DADEM1	DADEM0	DFS		MODE
			-----   ------  --- 	----
			0		0		0		44.1 kHz
			0		1		0		OFF
			1		0		0		48.0 kHz
			1		1		0		32 kHz
			0		0		1		OFF
			0		1		1		OFF
			1		0		1		96 kHz
			1		1		1		OFF
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */


.SEGMENT/PM	pm_code;
		/* program the ADCs and DACs via memory-mapped MS3 AD/DA Register */

Enable_AKM_Converters:
		/*  mute the DACs */
		ustat1 = DM(ADDA_CONFIG_REG);
		bit set ustat1 DAMUTE;
		DM(ADDA_CONFIG_REG) = ustat1;

		/* reset the ADCs and DACs */
		ustat1 = DM(ADDA_CONFIG_REG);
		bit clr ustat1 ANRST;
		DM(ADDA_CONFIG_REG) = ustat1;

		/* Hold ADCs and DACs LO for 150 nsec */
		LCNTR=9, DO reset_AKM_loop UNTIL LCE;
reset_AKM_loop:	NOP;

		/* bring A/D and D/A converters out of reset lo */
		ustat1 = DM(ADDA_CONFIG_REG);
		bit set ustat1 ANRST;
		DM(ADDA_CONFIG_REG) = ustat1;

		/* Set up ADCs & DACs for 96 KHz operation, enable ADC Hi-Pass Filter */
		ustat1 = DM(ADDA_CONFIG_REG);
		bit set ustat1 ADHPFE|DADEM1|DFS;
		bit clr ustat1 DADEM0;
		DM(ADDA_CONFIG_REG) = ustat1;

		/* enable the DAC outputs */
		ustat1 = DM(ADDA_CONFIG_REG);
		bit clr ustat1 DAMUTE;
		DM(ADDA_CONFIG_REG) = ustat1;

		RTS;

.ENDSEG;