tsi108_init.c

U-boot源码 ARM7启动代码

/*****************************************************************************
 * (C) Copyright 2003;  Tundra Semiconductor Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *****************************************************************************/

/*----------------------------------------------------------------------------
 * FILENAME: tsi108_init.c
 *
 * Originator: Alex Bounine
 *
 * DESCRIPTION:
 * Initialization code for the Tundra Tsi108 bridge chip
 *---------------------------------------------------------------------------*/

#include <common.h>
#include <74xx_7xx.h>
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <tsi108.h>

DECLARE_GLOBAL_DATA_PTR;

extern void mpicInit (int verbose);

/*
 * Configuration Options
 */

typedef struct {
	ulong upper;
	ulong lower;
} PB2OCN_LUT_ENTRY;

PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
	/* 0 - 7 */
	{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */

	/* 8 - 15 */
	{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */

	/* 16 - 23 */
	{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
	/* 24 - 31 */
	{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X  PCI I/O (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X  PCI Config (Byte-Swap) */

	{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
	{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
	{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
	{0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
};

#ifdef CFG_CLK_SPREAD
typedef struct {
	ulong ctrl0;
	ulong ctrl1;
} PLL_CTRL_SET;

/*
 * Clock Generator SPLL0 initialization values
 * PLL0 configuration table for various PB_CLKO freq.
 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
 */

static PLL_CTRL_SET pll0_config[8] = {
	{0x00000000, 0x00000000},	/* 0: bypass */
	{0x00000000, 0x00000000},	/* 1: reserved */
	{0x00430044, 0x00000043},	/* 2: CG_PB_CLKO = 183 MHz */
	{0x005c0044, 0x00000039},	/* 3: CG_PB_CLKO = 100 MHz */
	{0x005c0044, 0x00000039},	/* 4: CG_PB_CLKO = 133 MHz */
	{0x004a0044, 0x00000040},	/* 5: CG_PB_CLKO = 167 MHz */
	{0x005c0044, 0x00000039},	/* 6: CG_PB_CLKO = 200 MHz */
	{0x004f0044, 0x0000003e}	/* 7: CG_PB_CLKO = 233 MHz */
};
#endif	/* CFG_CLK_SPREAD */

/*
 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
 * (based on recommended Tsi108 reference clock 33MHz)
 */
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };

/*
 * get_board_bus_clk ()
 *
 * returns the bus clock in Hz.
 */
unsigned long get_board_bus_clk (void)
{
	ulong i;

	/* Detect PB clock freq. */
	i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */

	return pb_clk_sel[i] * 1000000;
}

/*
 * board_early_init_f ()
 *
 * board-specific initialization executed from flash
 */

int board_early_init_f (void)
{
	ulong i;

	gd->mem_clk = 0;
	i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
			CG_PWRUP_STATUS);
	i = (i >> 20) & 0x07;	/* Get GD PLL multiplier */
	switch (i) {
	case 0:	/* external clock */
		printf ("Using external clock\n");
		break;
	case 1:	/* system clock */
		gd->mem_clk = gd->bus_clk;
		break;
	case 4:	/* 133 MHz */
	case 5:	/* 166 MHz */
	case 6:	/* 200 MHz */
		gd->mem_clk = pb_clk_sel[i] * 1000000;
		break;
	default:
		printf ("Invalid DDR2 clock setting\n");
		return -1;
	}
	printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
	printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
	return 0;
}

/*
 * board_early_init_r() - Tsi108 initialization function executed right after
 * relocation. Contains code that cannot be executed from flash.
 */

int board_early_init_r (void)
{
	ulong temp, i;
	ulong reg_val;
	volatile ulong *reg_ptr;

	reg_ptr =
		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = 0x00000201;	/* SWAP ENABLED */
		*reg_ptr++ = 0x00;
	}

	__asm__ __volatile__ ("eieio");
	__asm__ __volatile__ ("sync");

	/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */

	out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
		0x80000001);
	__asm__ __volatile__ ("sync");

	/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
	 * read from SDRAM)
	 */

	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
	__asm__ __volatile__ ("sync");

	/*
	 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
	 * processor bus address space. Immediately after reset LUT and address
	 * translation are disabled for this BAR. Now we have to initialize LUT
	 * and switch from the BOOT mode to the normal operation mode.
	 *
	 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
	 * and covers 512MB of address space. To allow larger aperture we also
	 * have to relocate register window of Tsi108
	 *
	 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
	 * mode.
	 *
	 * initialize pointer to LUT associated with PB_OCN_BAR1
	 */
	reg_ptr =
		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = pb2ocn_lut1[i].lower;
		*reg_ptr++ = pb2ocn_lut1[i].upper;
	}

	__asm__ __volatile__ ("sync");

	/* Base addresses for CS0, CS1, CS2, CS3 */

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
		0x00000000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
		0x00100000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
		0x00200000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
		0x00300000);
	__asm__ __volatile__ ("sync");

	/* Masks for HLP banks */

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	/* Set CTRL0 values for banks */

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
		0x7FFC44C2);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
		0x7FFC44C0);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
		0x7FFC44C0);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
		0x7FFC44C2);
	__asm__ __volatile__ ("sync");

	/* Set banks to latched mode, enabled, and other default settings */

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	/*
	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
	 */
	out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
		0xE0000011);
	__asm__ __volatile__ ("sync");

	/* Make sure that OCN_BAR2 decoder is set (to allow following
	 * immediate read from SDRAM)
	 */

	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
	__asm__ __volatile__ ("sync");

	/*
	 * SRI: At this point we have enabled the HLP banks. That means we can
	 * now read from the NVRAM and initialize the environment variables.
	 * We will over-ride the env_init called in board_init_f
	 * This is really a work-around because, the HLP bank 1
	 * where NVRAM resides is not visible during board_init_f
	 * (lib_ppc/board.c)
	 * Alternatively, we could use the I2C EEPROM at start-up to configure
	 * and enable all HLP banks and not just HLP 0 as is being done for
	 * Taiga Rev. 2.
	 */

	env_init ();