sc3.c

U-boot源码 ARM7启动代码

			else
				if (s1[i] >= 'A' && s1[i] <= 'F')
					xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
				else
					if (s1[i] >= 'a' && s1[i] <= 'f')
						xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
					else {
						xilinx_val = -1;
						break;
					}
			i++;
		}
		if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
			printf ("Xilinx: set to %s\n", s1);
			*xilinx_adr = (unsigned char) xilinx_val;
		} else
			printf ("Xilinx: rejected value %s\n", s1);
	}
	return 0;
}

/* -------------------------------------------------------------------------
 * printCSConfig
 *
 * Print some informations about chips select configurations
 * Only used while debugging.
 *
 * Params:
 * - No. of CS pin
 * - AP of this CS
 * - CR of this CS
 *
 * Returns
 * nothing
   ------------------------------------------------------------------------- */

#ifdef SC3_DEBUGOUT
static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
{
	const char *bsize[4] = {"8","16","32","?"};
	const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
	const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};

#define CYCLE 30  /* time of one clock (based on 33MHz) */

	printf("\nCS#%d",reg);
	if (!(cr & 0x00018000))
		puts(" unused");
	else {
		if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
			puts(" Address is not multiple of bank size!");

		printf("\n -%s bit device",
			bsize[(cr & 0x00006000) >> 13]);
		printf(" at 0x%08lX", cr & 0xFFF00000U);
		printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
		printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
   	   	if (ap & 0x80000000) {
			printf("\n -Burst device (%luns/%luns)",
				(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
				(((ap & 0x03800000) >> 23) + 1) * CYCLE);
		} else {
			printf("\n -Non burst device, active cycle %luns",
				(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
			printf("\n -Address setup %luns",
				((ap & 0xC0000) >> 18) * CYCLE);
			printf("\n -CS active to RD %luns/WR %luns",
				((ap & 0x30000) >> 16) * CYCLE,
				((ap & 0xC000) >> 14) * CYCLE);
			printf("\n -WR to CS inactive %luns",
				((ap & 0x3000) >> 12) * CYCLE);
			printf("\n -Hold after access %luns",
				((ap & 0xE00) >> 9) * CYCLE);
			printf("\n -Ready is %sabled",
				ap & 0x100 ? "en" : "dis");
		}
	}
}
#endif

#ifdef SC3_DEBUGOUT

static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
				pb5ap, pb6ap, pb7ap};
static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
				pb5cr, pb6cr, pb7cr};

static int show_reg (int nr)
{
	unsigned long ul1, ul2;

	mtdcr (ebccfga, ap[nr]);
	ul1 = mfdcr (ebccfgd);
	mtdcr (ebccfga, cr[nr]);
	ul2 = mfdcr(ebccfgd);
	printCSConfig(nr, ul1, ul2);
	return 0;
}
#endif

int checkboard (void)
{
#ifdef SC3_DEBUGOUT
	unsigned long ul1;
	int	i;

	for (i = 0; i < 8; i++) {
		show_reg (i);
	}

	mtdcr (ebccfga, epcr);
	ul1 = mfdcr (ebccfgd);

	puts ("\nGeneral configuration:\n");

	if (ul1 & 0x80000000)
		printf(" -External Bus is always driven\n");

	if (ul1 & 0x400000)
		printf(" -CS signals are always driven\n");

	if (ul1 & 0x20000)
		printf(" -PowerDown after %lu clocks\n",
			(ul1 & 0x1F000) >> 7);

	switch (ul1 & 0xC0000)
	{
	case 0xC0000:
		printf(" -No external master present\n");
		break;
	case 0x00000:
		printf(" -8 bit external master present\n");
		break;
	case 0x40000:
		printf(" -16 bit external master present\n");
		break;
	case 0x80000:
		printf(" -32 bit external master present\n");
		break;
	}

	switch (ul1 & 0x300000)
	{
	case 0x300000:
		printf(" -Prefetch: Illegal setting!\n");
		break;
	case 0x000000:
		printf(" -1 doubleword prefetch\n");
		break;
	case 0x100000:
		printf(" -2 doublewords prefetch\n");
		break;
	case 0x200000:
		printf(" -4 doublewords prefetch\n");
		break;
	}
	putc ('\n');
#endif
	printf("Board: SolidCard III %s %s version.\n",
		(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
	return 0;
}

static int printSDRAMConfig(char reg, unsigned long cr)
{
	const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
#ifdef SC3_DEBUGOUT
	const char *basize[8]=
		{"4", "8", "16", "32", "64", "128", "256", "Reserved"};

	printf("SDRAM bank %d",reg);

	if (!(cr & 0x01))
		puts(" disabled\n");
	else {
		printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
		printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
	}
#endif

	if (cr & 0x01)
		return(bisize[(cr & 0xE0000) >> 17]);

	return 0;
}

#ifdef SC3_DEBUGOUT
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
#endif

long int initdram (int board_type)
{
	unsigned int mems=0;
	unsigned long ul1;

#ifdef SC3_DEBUGOUT
	unsigned long ul2;
	int	i;

	puts("\nSDRAM configuration:\n");

	mtdcr (memcfga, mem_mcopt1);
	ul1 = mfdcr(memcfgd);

	if (!(ul1 & 0x80000000)) {
		puts(" Controller disabled\n");
		return 0;
	}
	for (i = 0; i < 4; i++) {
		mtdcr (memcfga, mbcf[i]);
		ul1 = mfdcr (memcfgd);
		mems += printSDRAMConfig (i, ul1);
	}

	mtdcr (memcfga, mem_sdtr1);
	ul1 = mfdcr(memcfgd);

	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
	printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
	printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
	printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
	puts ("Misc:\n");
	mtdcr (memcfga, mem_rtr);
	ul1 = mfdcr(memcfgd);
	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);

	mtdcr(memcfga,mem_pmit);
	ul2=mfdcr(memcfgd);

	mtdcr(memcfga,mem_mcopt1);
	ul1=mfdcr(memcfgd);

	if (ul1 & 0x20000000)
		printf(" -Power Down after: %luns\n",
			((ul2 & 0xFFC00000) >> 22) * 7);
	else
		puts(" -Power Down disabled\n");

	if (ul1 & 0x40000000)
		printf(" -Self refresh feature active\n");
	else
		puts(" -Self refresh disabled\n");

	if (ul1 & 0x10000000)
		puts(" -ECC enabled\n");
	else
		puts(" -ECC disabled\n");

	if (ul1 & 0x8000000)
		puts(" -Using registered SDRAM\n");

	if (!(ul1 & 0x6000000))
		puts(" -Using 32 bit data width\n");
	else
		puts(" -Illegal data width!\n");

	if (ul1 & 0x400000)
		puts(" -ECC drivers inactive\n");
	else
		puts(" -ECC drivers active\n");

	if (ul1 & 0x200000)
		puts(" -Memory lines always active outputs\n");
	else
		puts(" -Memory lines only at write cycles active outputs\n");

	mtdcr (memcfga, mem_status);
	ul1 = mfdcr (memcfgd);
	if (ul1 & 0x80000000)
		puts(" -SDRAM Controller ready\n");
	else
		puts(" -SDRAM Controller not ready\n");

	if (ul1 & 0x4000000)
		puts(" -SDRAM in self refresh mode!\n");

	return (mems * 1024 * 1024);
#else
	mtdcr (memcfga, mem_mb0cf);
	ul1 = mfdcr (memcfgd);
	mems = printSDRAMConfig (0, ul1);

	mtdcr (memcfga, mem_mb1cf);
	ul1 = mfdcr (memcfgd);
	mems += printSDRAMConfig (1, ul1);

	mtdcr (memcfga, mem_mb2cf);
	ul1 = mfdcr(memcfgd);
	mems += printSDRAMConfig (2, ul1);

	mtdcr (memcfga, mem_mb3cf);
	ul1 = mfdcr(memcfgd);
	mems += printSDRAMConfig (3, ul1);

	return (mems * 1024 * 1024);
#endif
}

static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
/*-------------------------------------------------------------------------+
 |             ,-.     ,-.        ,-.        ,-.        ,-.
 |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
 |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
 |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
 |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
 |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
 |             |E|     |+| /\     |+| /\     |r| /\     |k|
 |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
 |             `-'     `-'        `-'        `-'        `-'
 |   Slot      0       10         11         12         13
 |   REQ#              0          1          2          *
 |   GNT#              0          1          2          *
 +-------------------------------------------------------------------------*/
	unsigned char int_line = 0xff;

	switch (PCI_DEV(dev)) {
	case 10:
		int_line = 31; /* INT A */
		POST_OUT(0x42);
		break;

	case 11:
		int_line = 30; /* INT B */
		POST_OUT(0x43);
		break;

	case 12:
		int_line = 29; /* INT C */
		POST_OUT(0x44);
		break;

	case 13:
		int_line = 28; /* INT D */
		POST_OUT(0x45);
		break;
	}
	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}

extern void pci_405gp_init(struct pci_controller *hose);
extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
/*
 * The following table is used when there is a special need to setup a PCI device.
 * For every PCI device found in this table is called the given init function with given
 * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
 * parameters!
 *
*/
static struct pci_config_table pci_solidcard3_config_table[] =
{
/* Host to PCI Bridge device (405GP) */
	{
		vendor: 0x1014,
		device: 0x0156,
		class: PCI_CLASS_BRIDGE_HOST,
		bus: 0,
		dev: 0,
		func: 0,
		config_device: pci_405gp_setup_bridge
	},
	{ }
};

/*-------------------------------------------------------------------------+
 | pci_init_board (Called from pci_init() in drivers/pci.c)
 |
 | Init the PCI part of the SolidCard III
 |
 | Params:
 * - Pointer to current PCI hose
 * - Current Device
 *
 * Returns
 * nothing
 +-------------------------------------------------------------------------*/

void pci_init_board(void)
{
	POST_OUT(0x41);
/*
 * we want the ptrs to RAM not flash (ie don't use init list)
 */
	hose.fixup_irq    = pci_solidcard3_fixup_irq;
	hose.config_table = pci_solidcard3_config_table;
	pci_405gp_init(&hose);
}