tqm8272.c

U-boot源码 ARM7启动代码

		case 'B': hw->buscl = 66666666;
			break;
		case 'E': hw->buscl = 100000000;
			break;
		case 'F': hw->buscl = 133333333;
			break;
		default:
			deb_printf("No BUS Clk\n");
			return -7;
			break;
	}
	p++;

	hw->OK = 1;
	/* search MAC Address */
	while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
		if (*p < ' ' || *p > '~') { /* ASCII strings! */
			return 0;
		}
		switch (part) {
		default:
			if (*p == ' ') {
				++part;
				i = 0;
			}
			break;
		case 3:			/* Copy MAC address */
			if (*p == ' ') {
				++part;
				i = 0;
				break;
			}
			hw->ethaddr[i++] = *p;
			if ((i % 3) == 2)
				hw->ethaddr[i++] = ':';
			break;

		}
		p++;
	}

	hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
	return 0;
}

#if defined(CONFIG_GET_CPU_STR_F)
/* !! This routine runs from Flash */
char get_cpu_str_f (char *buf)
{
	char *p = (char *) HWIB_INFO_START_ADDR;
	int	i = 0;

	buf[i++] = 'M';
	buf[i++] = 'P';
	buf[i++] = 'C';
	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
		buf[i++] = *&p[3];
		buf[i++] = *&p[4];
		buf[i++] = *&p[5];
		buf[i++] = *&p[6];
	} else {
		buf[i++] = '8';
		buf[i++] = '2';
		buf[i++] = '7';
		buf[i++] = 'x';
	}
	buf[i++] = 0;
	return 0;
}
#endif

#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
/* !! This routine runs from Flash */
unsigned long board_get_cpu_clk_f (void)
{
	char *p = (char *) HWIB_INFO_START_ADDR;
	int i = 0;

	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
		if (search_real_busclk (&i))
			return i;
	}
	return CONFIG_8260_CLKIN;
}
#endif

#if CONFIG_BOARD_EARLY_INIT_R

static int can_test (unsigned long off)
{
	volatile unsigned char	*base	= (unsigned char *) (CFG_CAN_BASE + off);

	*(base + 0x17) = 'T';
	*(base + 0x18) = 'Q';
	*(base + 0x19) = 'M';
	if ((*(base + 0x17) != 'T') ||
	    (*(base + 0x18) != 'Q') ||
	    (*(base + 0x19) != 'M')) {
		return 0;
	}
	return 1;
}

static int can_config_one (unsigned long off)
{
	volatile unsigned char	*ctrl	= (unsigned char *) (CFG_CAN_BASE + off);
	volatile unsigned char	*cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
	volatile unsigned char	*clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
	unsigned char temp;

	*cpu_if = 0x45;
	temp = *ctrl;
	temp |= 0x40;
	*ctrl	= temp;
	*clkout = 0x20;
	temp = *ctrl;
	temp &= ~0x40;
	*ctrl	= temp;
	return 0;
}

static int can_config (void)
{
	int	ret = 0;
	can_config_one (0);
	if (hwinf.can == 2) {
		can_config_one (0x100);
	}
	/* make Test if they really there */
	ret += can_test (0);
	ret += can_test (0x100);
	return ret;
}

static int init_can (void)
{
	volatile immap_t * immr = (immap_t *)CFG_IMMR;
	volatile memctl8260_t *memctl = &immr->im_memctl;
	int	count = 0;

	if ((hwinf.OK) && (hwinf.can)) {
		memctl->memc_or4 = CFG_CAN_OR;
		memctl->memc_br4 = CFG_CAN_BR;
		/* upm Init */
		upmconfig (UPMC, (uint *) upmTableFast,
			   sizeof (upmTableFast) / sizeof (uint));
		memctl->memc_mcmr =	(MxMR_DSx_3_CYCL |
					MxMR_GPL_x4DIS |
					MxMR_RLFx_2X |
					MxMR_WLFx_2X |
					MxMR_OP_NORM);
		/* can configure */
		count = can_config ();
		printf ("CAN:	%d @ %x\n", count, CFG_CAN_BASE);
		if (hwinf.can != count) printf("!!! difference to HWIB\n");
	} else {
		printf ("CAN:	No\n");
	}
	return 0;
}

int board_early_init_r(void)
{
	analyse_hwib ();
	init_can ();
	return 0;
}
#endif

int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	dump_hwib ();
	return 0;
}

U_BOOT_CMD(
	  hwib, 1,	1,	do_hwib_dump,
	  "hwib	   - dump HWIB'\n",
	  "\n"
);

#ifdef CFG_UPDATE_FLASH_SIZE
static int get_flash_timing (void)
{
	/* get it from the option -tf in CIB */
	/* default is 0x00000c84 */
	int	ret = 0x00000c84;
	int	pos = 0;
	int	nr = 0;
	char	*p = (char *) CIB_INFO_START_ADDR;

	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
		if (*p < ' ' || *p > '~') { /* ASCII strings! */
			return ret;
		}
		if (*p == '-') {
			if ((p[1] == 't') && (p[2] == 'f')) {
				p += 6;
				ret = 0;
				while (nr < 8) {
				if ((*p >= '0') && (*p <= '9')) {
					ret *= 0x10;
					ret += *p - '0';
					p += 1;
					nr ++;
				} else if ((*p >= 'A') && (*p <= 'F')) {
					ret *= 10;
					ret += *p - '7';
					p += 1;
					nr ++;
				} else {
					if (nr < 8) return 0x00000c84;
					return ret;
				}
				}
			}
		}
		p++;
		pos++;
	}
	return ret;
}

/* Update the Flash_Size and the Flash Timing */
int update_flash_size (int flash_size)
{
	volatile immap_t * immr = (immap_t *)CFG_IMMR;
	volatile memctl8260_t *memctl = &immr->im_memctl;
	unsigned long reg;
	unsigned long tim;

	/* I must use reg, otherwise the board hang */
	reg = memctl->memc_or0;
	reg &= ~ORxU_AM_MSK;
	reg |= MEG_TO_AM(flash_size >> 20);
	tim = get_flash_timing ();
	reg &= ~0xfff;
	reg |= (tim & 0xfff);
	memctl->memc_or0 = reg;
	return 0;
}
#endif

#if defined(CONFIG_CMD_NAND)

#include <nand.h>
#include <linux/mtd/mtd.h>

static u8 hwctl = 0;

static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
{
	switch (cmd) {
	case NAND_CTL_SETCLE:
		hwctl |= 0x1;
		break;
	case NAND_CTL_CLRCLE:
		hwctl &= ~0x1;
		break;

	case NAND_CTL_SETALE:
		hwctl |= 0x2;
		break;

	case NAND_CTL_CLRALE:
		hwctl &= ~0x2;
		break;
	}
}

static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
	struct nand_chip *this = mtdinfo->priv;
	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);

	if (hwctl & 0x1) {
		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
	} else if (hwctl & 0x2) {
		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
	} else {
		WRITE_NAND(byte, base);
	}
}

static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
{
	struct nand_chip *this = mtdinfo->priv;
	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);

	return READ_NAND(base);
}

static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
{
	/* constant delay (see also tR in the datasheet) */
	udelay(12); \
	return 1;
}

#ifndef CONFIG_NAND_SPL
static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
	struct nand_chip *this = mtdinfo->priv;
	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
	int	i;

	for (i = 0; i< len; i++)
		buf[i] = *base;
}

static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
	struct nand_chip *this = mtdinfo->priv;
	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
	int	i;

	for (i = 0; i< len; i++)
		*base = buf[i];
}

static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
	struct nand_chip *this = mtdinfo->priv;
	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
	int	i;

	for (i = 0; i < len; i++)
		if (buf[i] != *base)
			return -1;
	return 0;
}
#endif /* #ifndef CONFIG_NAND_SPL */

void board_nand_select_device(struct nand_chip *nand, int chip)
{
	chipsel = chip;
}

int board_nand_init(struct nand_chip *nand)
{
	static	int	UpmInit = 0;
	volatile immap_t * immr = (immap_t *)CFG_IMMR;
	volatile memctl8260_t *memctl = &immr->im_memctl;

	if (hwinf.nand == 0) return -1;

	/* Setup the UPM */
	if (UpmInit == 0) {
		switch (hwinf.busclk_real) {
		case 100000000:
			upmconfig (UPMB, (uint *) upmTable100,
			   sizeof (upmTable100) / sizeof (uint));
			break;
		case 133333333:
			upmconfig (UPMB, (uint *) upmTable133,
			   sizeof (upmTable133) / sizeof (uint));
			break;
		default:
			upmconfig (UPMB, (uint *) upmTable67,
			   sizeof (upmTable67) / sizeof (uint));
			break;
		}
		UpmInit = 1;
	}

	/* Setup the memctrl */
	memctl->memc_or3 = CFG_NAND_OR;
	memctl->memc_br3 = CFG_NAND_BR;
	memctl->memc_mbmr = (MxMR_OP_NORM);

	nand->eccmode = NAND_ECC_SOFT;

	nand->hwcontrol	 = upmnand_hwcontrol;
	nand->read_byte	 = upmnand_read_byte;
	nand->write_byte = upmnand_write_byte;
	nand->dev_ready	 = tqm8272_dev_ready;

#ifndef CONFIG_NAND_SPL
	nand->write_buf	 = tqm8272_write_buf;
	nand->read_buf	 = tqm8272_read_buf;
	nand->verify_buf = tqm8272_verify_buf;
#endif

	/*
	 * Select required NAND chip
	 */
	board_nand_select_device(nand, 0);
	return 0;
}

#endif

#ifdef CONFIG_PCI
struct pci_controller hose;

int board_early_init_f (void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;

	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
	return 0;
}

extern void pci_mpc8250_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc8250_init(&hose);
}
#endif