tqm8272.c

U-boot源码 ARM7启动代码

	/* default is 3 */
	int	ret = 3;
	int	pos = 0;
	char	*p = (char *) CIB_INFO_START_ADDR;

	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
		if (*p < ' ' || *p > '~') { /* ASCII strings! */
			return ret;
		}
		if (*p == '-') {
			if ((p[1] == 't') && (p[2] == 's')) {
				return (p[4] - '0');
			}
		}
		p++;
		pos++;
	}
	return ret;
}
#endif

static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
{
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	int	clk = board_get_cpu_clk_f ();
	volatile immap_t *immr = (immap_t *)CFG_IMMR;
	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
	int	cas;

	sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
			 PSDMR_BUFCMD);
	if (busmode) {
		switch (clk) {
			case 66666666:
				sdmr |= (PSDMR_RFRC_66MHZ_60X | \
					PSDMR_PRETOACT_66MHZ_60X | \
					PSDMR_WRC_66MHZ_60X | \
					PSDMR_BUFCMD_66MHZ_60X);
				break;
			case 100000000:
				sdmr |= (PSDMR_RFRC_100MHZ_60X | \
					PSDMR_PRETOACT_100MHZ_60X | \
					PSDMR_WRC_100MHZ_60X | \
					PSDMR_BUFCMD_100MHZ_60X);
				break;

		}
	} else {
		switch (clk) {
			case 66666666:
				sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
					PSDMR_PRETOACT_66MHZ_SINGLE | \
					PSDMR_WRC_66MHZ_SINGLE | \
					PSDMR_BUFCMD_66MHZ_SINGLE);
				break;
			case 100000000:
				sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
					PSDMR_PRETOACT_100MHZ_SINGLE | \
					PSDMR_WRC_100MHZ_SINGLE | \
					PSDMR_BUFCMD_100MHZ_SINGLE);
				break;
			case 133333333:
				sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
					PSDMR_PRETOACT_133MHZ_SINGLE | \
					PSDMR_WRC_133MHZ_SINGLE | \
					PSDMR_BUFCMD_133MHZ_SINGLE);
				break;
		}
	}
	cas = get_cas_latency();
	sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
	sdmr |= cas;
	sdmr |= ((cas - 1) << 6);
	return sdmr;
#else
	return sdmr;
#endif
}

/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 *
 * This routine performs standard 8260 initialization sequence
 * and calculates the available memory size. It may be called
 * several times to try different SDRAM configurations on both
 * 60x and local buses.
 */
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
						  ulong orx, volatile uchar * base, int col)
{
	volatile uchar c = 0xff;
	volatile uint *sdmr_ptr;
	volatile uint *orx_ptr;
	ulong maxsize, size;
	int i;

	/* We must be able to test a location outsize the maximum legal size
	 * to find out THAT we are outside; but this address still has to be
	 * mapped by the controller. That means, that the initial mapping has
	 * to be (at least) twice as large as the maximum expected size.
	 */
	maxsize = (1 + (~orx | 0x7fff)) / 2;

	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
	 * we are configuring CS1 if base != 0
	 */
	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;

	*orx_ptr = orx;
	sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
	 */

	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
	*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
		*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */

	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*base = c;

	size = get_ram_size((long *)base, maxsize);
	*orx_ptr = orx | ~(size - 1);

	return (size);
}

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;

#ifndef CFG_RAMBOOT
	long size8, size9;
#endif
	long psize, lsize;

	psize = 16 * 1024 * 1024;
	lsize = 0;

	memctl->memc_psrt = CFG_PSRT;
	memctl->memc_mptpr = CFG_MPTPR;

#ifndef CFG_RAMBOOT
	/* 60x SDRAM setup:
	 */
	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
					  (uchar *) CFG_SDRAM_BASE, 8);
	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
					  (uchar *) CFG_SDRAM_BASE, 9);

	if (size8 < size9) {
		psize = size9;
		printf ("(60x:9COL - %ld MB, ", psize >> 20);
	} else {
		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
						  (uchar *) CFG_SDRAM_BASE, 8);
		printf ("(60x:8COL - %ld MB, ", psize >> 20);
	}

#endif /* CFG_RAMBOOT */

	icache_enable ();

	return (psize);
}


static inline int scanChar (char *p, int len, unsigned long *number)
{
	int	akt = 0;

	*number = 0;
	while (akt < len) {
		if ((*p >= '0') && (*p <= '9')) {
			*number *= 10;
			*number += *p - '0';
			p += 1;
		} else {
			if (*p == '-')	return akt;
			return -1;
		}
		akt ++;
	}
	return akt;
}

typedef struct{
	int	Bus;
	int	flash;
	int	flash_nr;
	int	ram;
	int	ram_cs;
	int	nand;
	int	nand_cs;
	int	eeprom;
	int	can;
	unsigned long	cpunr;
	unsigned long	option;
	int	SecEng;
	int	cpucl;
	int	cpmcl;
	int	buscl;
	int	busclk_real_ok;
	int	busclk_real;
	unsigned char	OK;
	unsigned char  ethaddr[20];
} HWIB_INFO;

HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
			 0, 0, 0, 0, 0, 0};

static int dump_hwib(void)
{
	HWIB_INFO	*hw = &hwinf;
	volatile immap_t *immr = (immap_t *)CFG_IMMR;
	char *s = getenv("serial#");

	if (hw->OK) {
		printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
		printf ("serial : %s\n", s);
		printf ("ethaddr: %s\n", hw->ethaddr);
		printf ("FLASH	: %x nr:%d\n", hw->flash, hw->flash_nr);
		printf ("RAM	: %x cs:%d\n", hw->ram, hw->ram_cs);
		printf ("CPU	: %d\n", hw->cpunr);
		printf ("CAN	: %d\n", hw->can);
		if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
		else printf ("No EEprom\n");
		if (hw->nand) {
			printf ("NAND	: %x\n", hw->nand);
			printf ("NAND CS: %d\n", hw->nand_cs);
		} else { printf ("No NAND\n");}
		printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
		printf ("  real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
				 "60x" : "Single PQII"));
		printf ("Option : %x\n", hw->option);
		printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
		printf ("CPM Clk: %d\n", hw->cpmcl);
		printf ("CPU Clk: %d\n", hw->cpucl);
		printf ("Bus Clk: %d\n", hw->buscl);
		if (hw->busclk_real_ok) {
			printf ("  real Clk: %d\n", hw->busclk_real);
		}
		printf ("CAS	: %d\n", get_cas_latency());
	} else {
		printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
	}
	return 0;
}

static inline int search_real_busclk (int *clk)
{
	int	part = 0, pos = 0;
	char *p = (char *) CIB_INFO_START_ADDR;
	int	ok = 0;

	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
		if (*p < ' ' || *p > '~') { /* ASCII strings! */
			return 0;
		}
		switch (part) {
		default:
			if (*p == '-') {
				++part;
			}
			break;
		case 3:
			if (*p == '-') {
				++part;
				break;
			}
			if (*p == 'b') {
				ok = 1;
				p++;
				break;
			}
			if (ok) {
				switch (*p) {
				case '6':
					*clk = 66666666;
					return 1;
					break;
				case '1':
					if (p[1] == '3') {
						*clk = 133333333;
					} else {
						*clk = 100000000;
					}
					return 1;
					break;
				}
			}
			break;
		}
		p++;
	}
	return 0;
}

int analyse_hwib (void)
{
	char	*p = (char *) HWIB_INFO_START_ADDR;
	int	anz;
	int	part = 1, i = 0, pos = 0;
	HWIB_INFO	*hw = &hwinf;

	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
	/* Head = TQM */
	if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
		deb_printf("No HWIB\n");
		return -1;
	}
	p += 3;
	if (scanChar (p, 4, &hw->cpunr) < 0) {
		deb_printf("No CPU\n");
		return -2;
	}
	p +=4;

	hw->flash = 0x200000 << (*p - 'A');
	p++;
	hw->flash_nr = *p - '0';
	p++;

	hw->ram = 0x2000000 << (*p - 'A');
	p++;
	if (*p == '2') {
		hw->ram_cs = 2;
		p++;
	}

	if (*p == 'A') hw->can = 1;
	if (*p == 'B') hw->can = 2;
	p +=1;
	p +=1;	/* connector */
	if (*p != '0') {
		hw->eeprom = 0x1000 << (*p - 'A');
	}
	p++;

	if ((*p < '0') || (*p > '9')) {
		/* NAND before z-option */
		hw->nand = 0x8000000 << (*p - 'A');
		p++;
		hw->nand_cs = *p - '0';
		p += 2;
	}
	/* z-option */
	anz = scanChar (p, 4, &hw->option);
	if (anz < 0) {
		deb_printf("No option\n");
		return -3;
	}
	if (hw->option & 0x8) hw->Bus = 1;
	p += anz;
	if (*p != '-') {
		deb_printf("No -\n");
		return -4;
	}
	p++;
	/* C option */
	if (*p == 'E') {
		hw->SecEng = 1;
		p++;
	}
	switch (*p) {
		case 'M': hw->cpucl = 266666666;
			break;
		case 'P': hw->cpucl = 300000000;
			break;
		case 'T': hw->cpucl = 400000000;
			break;
		default:
			deb_printf("No CPU Clk: %c\n", *p);
			return -5;
			break;
	}
	p++;
	switch (*p) {
		case 'I': hw->cpmcl = 200000000;
			break;
		case 'M': hw->cpmcl = 300000000;
			break;
		default:
			deb_printf("No CPM Clk\n");
			return -6;
			break;
	}
	p++;
	switch (*p) {