pcs440ep.c

来自「U-boot源码 ARM7启动代码」· C语言 代码 · 共 918 行 · 第 1/2 页

		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CFG_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[1]);

	/* Env protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    CFG_ENV_ADDR_REDUND,
			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
			    &flash_info[1]);

	pcs440ep_readinputs ();
	pcs440ep_checksha1 ();
#ifdef CONFIG_PREBOOT
	{
		struct kbd_data_t kbd_data;
		/* Decode keys */
		char *str = strdup (key_match (get_keys (&kbd_data)));
		/* Set or delete definition */
		setenv ("preboot", str);
		free (str);
	}
#endif /* CONFIG_PREBOOT */
	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: PCS440EP");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

void spd_ddr_init_hang (void)
{
	status_led_set (0, STATUS_LED_OFF);
	status_led_set (1, STATUS_LED_ON);
	/* we cannot use hang() because we are still running from
	   Flash, and so the status_led driver is not initialized */
	puts ("### SDRAM ERROR ### Please RESET the board ###\n");
	for (;;) {
		__led_toggle (4);
		udelay (100000);
	}
}

long int initdram (int board_type)
{
	long dram_size = 0;

	status_led_set (0, STATUS_LED_ON);
	status_led_set (1, STATUS_LED_OFF);
	dram_size = spd_sdram();
	status_led_set (0, STATUS_LED_OFF);
	status_led_set (1, STATUS_LED_ON);
	if (dram_size == 0) {
		hang();
	}

	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif	/* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CFG_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* PCS440EP is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif

/*************************************************************************
 * "led" Commando for the U-Boot shell
 *
 ************************************************************************/
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int	rcode = 0, i;
	ulong	pattern = 0;

	pattern = simple_strtoul (argv[1], NULL, 16);
	if (pattern > 0x400) {
		int	val = GET_LEDS;
		printf ("led: %x\n", val);
		return rcode;
	}
	if (pattern > 0x200) {
		status_led_blink ();
		hang ();
		return rcode;
	}
	if (pattern > 0x100) {
		status_led_blink ();
		return rcode;
	}
	pattern &= 0x0f;
	for (i = 0; i < 4; i++) {
		if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
		else status_led_set (i, STATUS_LED_OFF);
		pattern = pattern >> 1;
	}
	return rcode;
}

U_BOOT_CMD(
 	led,	2,	1,	do_led,
 	"led [bitmask]   - set the DIAG-LED\n",
	"[bitmask] 0x01 = DIAG 1 on\n"
	"              0x02 = DIAG 2 on\n"
	"              0x04 = DIAG 3 on\n"
	"              0x08 = DIAG 4 on\n"
	"              > 0x100 set the LED, who are on, to state blinking\n"
);

#if defined(CONFIG_SHA1_CHECK_UB_IMG)
/*************************************************************************
 * "sha1" Commando for the U-Boot shell
 *
 ************************************************************************/
int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int	rcode = -1;

	if (argc < 2) {
  usage:
		printf ("Usage:\n%s\n", cmdtp->usage);
		return 1;
	}

	if (argc >= 3) {
		unsigned char *data;
		unsigned char output[20];
		int	len;
		int	i;

		data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
		len = simple_strtoul (argv[2], NULL, 16);
		sha1_csum (data, len, (unsigned char *)output);
		printf ("U-Boot sum:\n");
		for (i = 0; i < 20 ; i++) {
			printf ("%02X ", output[i]);
		}
		printf ("\n");
		if (argc == 4) {
			data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
			memcpy (data, output, 20);
		}
		return 0;
	}
	if (argc == 2) {
		char *ptr = argv[1];
		if (*ptr != '-') goto usage;
		ptr++;
		if ((*ptr == 'c') || (*ptr == 'C')) {
			rcode = pcs440ep_sha1 (1);
			printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
		} else if ((*ptr == 'p') || (*ptr == 'P')) {
			rcode = pcs440ep_sha1 (2);
		} else {
			rcode = pcs440ep_sha1 (0);
		}
		return rcode;
	}
	return rcode;
}

U_BOOT_CMD(
 	sha1,	4,	1,	do_sha1,
 	"sha1    - calculate the SHA1 Sum\n",
	"address len [addr]  calculate the SHA1 sum [save at addr]\n"
	"     -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
	"     -c check the U-Boot image in flash\n"
);
#endif

#if defined (CONFIG_CMD_IDE)
/* These addresses need to be shifted one place to the left
 * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
 * These values are shifted
 */
extern ulong *ide_bus_offset;
void inline ide_outb(int dev, int port, unsigned char val)
{
	debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
		dev, port, val, (ATA_CURR_BASE(dev)+port));

	out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
}
unsigned char inline ide_inb(int dev, int port)
{
	uchar val;
	val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
	debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
		dev, port, (ATA_CURR_BASE(dev)+port), val);
	return (val);
}
#endif

#ifdef CONFIG_IDE_PREINIT
int ide_preinit (void)
{
	/* Set True IDE Mode */
	out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
	out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
	out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
	udelay (100000);
	return 0;
}
#endif

#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);
	if (idereset == 0) {
		out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
	} else {
		out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
	}
	udelay (10000);
}
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */