start.s

U-boot源码 ARM7启动代码

/*
 * Copyright (C) 1998  Dan Malek <[e-mail]>
 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <[e-mail]>
 * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Based on the MPC83xx code.
 */

/*
 *  U-Boot - Startup Code for MPC512x based Embedded Boards
 */

#include <config.h>
#include <mpc512x.h>
#include <version.h>

#define CONFIG_521X	1		/* needed for Linux kernel header files*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING "MPC512X"
#endif

/*
 * Floating Point enable, Machine Check and Recoverable Interr.
 */
#undef	MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif

/* Macros for manipulating CSx_START/STOP */
#define START_REG(start)	((start) >> 16)
#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)

/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * Magic number and version string
 */
	.long	0x27051956		/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii " ", CONFIG_IDENT_STRING, "\0"

/*
 * Vector Table
 */
	.text
	. = EXC_OFF_SYS_RESET

	.globl	_start
	/* Start from here after reset/power on */
_start:
	li	r21, BOOTFLAG_COLD  /* Normal Power-On: Boot from FLASH */
	b	boot_cold

	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Floating Point Unit unavailable exception */
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

/* Decrementer */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)

/* Critical interrupt */
	STD_EXCEPTION(0xa00, Critical, UnknownException)

/* System Call */
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)

/* Trace interrupt */
	STD_EXCEPTION(0xd00, Trace, UnknownException)

/* Performance Monitor interrupt */
	STD_EXCEPTION(0xf00, PerfMon, UnknownException)

/* Intruction Translation Miss */
	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)

/* Data Load Translation Miss */
	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)

/* Data Store Translation Miss */
	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)

/* Instruction Address Breakpoint */
	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)

/* System Management interrupt */
	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)

	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000
boot_cold:
	/* Save msr contents */
	mfmsr	r5

	/* Set IMMR area to our preferred location */
	lis	r4, CONFIG_DEFAULT_IMMR@h
	lis	r3, CFG_IMMR@h
	ori	r3, r3, CFG_IMMR@l
	stw	r3, IMMRBAR(r4)
	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */

	/* Initialise the machine */
	bl	cpu_early_init

	/*
	 * Set up Local Access Windows:
	 *
	 * 1) Boot/CS0 (boot FLASH)
	 * 2) On-chip SRAM (initial stack purposes)
	 */

	/* Boot CS/CS0 window range */
	lis     r3, CFG_IMMR@h
	ori     r3, r3, CFG_IMMR@l

	lis	r4, START_REG(CFG_FLASH_BASE)
	ori	r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
	stw	r4, LPCS0AW(r3)

	/*
	 * The SRAM window has a fixed size (256K), so only the start address
	 * is necessary
	 */
	lis 	r4, START_REG(CFG_SRAM_BASE) & 0xff00
	stw	r4, SRAMBAR(r3)

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lwz	r4, SRAMBAR(r3)
	isync

	/*
	 * Set configuration of the Boot/CS0, the SRAM window does not have a
	 * config register so no params can be set for it
	 */
	lis     r3, (CFG_IMMR + LPC_OFFSET)@h
	ori     r3, r3, (CFG_IMMR + LPC_OFFSET)@l

	lis     r4, CFG_CS0_CFG@h
	ori     r4, r4, CFG_CS0_CFG@l
	stw     r4, CS0_CONFIG(r3)

	/* Master enable all CS's */
	lis	r4, CS_CTRL_ME@h
	ori	r4, r4, CS_CTRL_ME@l
	stw	r4, CS_CTRL(r3)

	lis	r4, (CFG_MONITOR_BASE)@h
	ori	r4, r4, (CFG_MONITOR_BASE)@l
	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r5
	blr

in_flash:
	lis	r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l

	li	r0, 0		/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest			*/
	/*							*/
	/* Be careful to keep code relocatable & stack humble	*/
	/*------------------------------------------------------*/

	GET_GOT			/* initialize GOT access	*/

	/* r3: IMMR */
	lis	r3, CFG_IMMR@h
	/* run low-level CPU init code (in Flash) */
	bl	cpu_init_f

	/* r3: BOOTFLAG */
	mr	r3, r21
	/* run 1st part of board init code (in Flash) */
	bl	board_init_f

	/* NOTREACHED - board_init_f() does not return */

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/*
 * This code initialises the machine, it expects original MSR contents to be in r5.
 */
cpu_early_init:
	/* Initialize machine status; enable machine check interrupt */
	/*-----------------------------------------------------------*/

	li	r3, MSR_KERNEL			/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
#ifdef DEBUG
	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
#endif
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */

	lis	r3, CFG_IMMR@h

#if defined(CONFIG_WATCHDOG)
	/* Initialise the watchdog and reset it */
	/*--------------------------------------*/
	lis r4, CFG_WATCHDOG_VALUE
	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
	stw r4, SWCRR(r3)

	/* reset */
	li	r4, 0x556C
	sth	r4, SWSRR@l(r3)
	li	r4, 0x0
	ori	r4, r4, 0xAA39
	sth	r4, SWSRR@l(r3)
#else
	/* Disable the watchdog */
	/*----------------------*/
	lwz r4, SWCRR(r3)
	/*
	 * Check to see if it's enabled for disabling: once disabled by s/w
	 * it's not possible to re-enable it
	 */
	andi. r4, r4, 0x4
	beq 1f
	xor r4, r4, r4
	stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */

	/* Initialize the Hardware Implementation-dependent Registers */
	/* HID0 also contains cache control			*/
	/*------------------------------------------------------*/
	lis	r3, CFG_HID0_INIT@h
	ori	r3, r3, CFG_HID0_INIT@l
	SYNC