ppc405.h

U-boot源码 ARM7启动代码

 *-------------------------------------------------------------------------------
 */
#define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
			    PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			    PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
			    PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			    PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)

#define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)

/*
 * PLL Voltage Controlled Oscillator (VCO) definitions
 * Maximum and minimum values (in MHz) for correct PLL operation.
 */
#define VCO_MIN     500
#define VCO_MAX     1000
#elif defined(CONFIG_405EZ)
/******************************************************************************
 * SDR Registers
 ******************************************************************************/
#define SDR_DCR_BASE 0x0E
#define sdrcfga (SDR_DCR_BASE+0x0)	/* ADDR */
#define sdrcfgd (SDR_DCR_BASE+0x1)	/* Data */

#define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)

#define sdrnand0	0x4000
#define sdrultra0	0x4040
#define sdrultra1	0x4050
#define sdricintstat	0x4510

#define SDR_NAND0_NDEN		0x80000000
#define SDR_NAND0_NDBTEN	0x40000000
#define SDR_NAND0_NDBADR_MASK	0x30000000
#define SDR_NAND0_NDBPG_MASK	0x0f000000
#define SDR_NAND0_NDAREN	0x00800000
#define SDR_NAND0_NDRBEN	0x00400000

#define SDR_ULTRA0_NDGPIOBP	0x80000000
#define SDR_ULTRA0_CSN_MASK	0x78000000
#define SDR_ULTRA0_CSNSEL0	0x40000000
#define SDR_ULTRA0_CSNSEL1	0x20000000
#define SDR_ULTRA0_CSNSEL2	0x10000000
#define SDR_ULTRA0_CSNSEL3	0x08000000
#define SDR_ULTRA0_EBCRDYEN	0x04000000
#define SDR_ULTRA0_SPISSINEN	0x02000000
#define SDR_ULTRA0_NFSRSTEN	0x01000000

#define SDR_ULTRA1_LEDNENABLE	0x40000000

#define SDR_ICRX_STAT	0x80000000
#define SDR_ICTX0_STAT	0x40000000
#define SDR_ICTX1_STAT	0x20000000

#define SDR_PINSTP	0x40

/******************************************************************************
 * Control
 ******************************************************************************/
#define CNTRL_DCR_BASE 0x0C
#define cprcfga (CNTRL_DCR_BASE+0x0)   /* CPR addr reg     */
#define cprcfgd (CNTRL_DCR_BASE+0x1)   /* CPR data reg     */

/* CPR Registers */
#define cprclkupd       0x020		/* CPR_CLKUPD */
#define cprpllc         0x040		/* CPR_PLLC */
#define cprplld         0x060		/* CPR_PLLD */
#define cprprimad       0x080		/* CPR_PRIMAD */
#define cprperd0        0x0e0		/* CPR_PERD0 */
#define cprperd1        0x0e1		/* CPR_PERD1 */
#define cprperc0        0x180		/* CPR_PERC0 */
#define cprmisc0        0x181		/* CPR_MISC0 */
#define cprmisc1        0x182		/* CPR_MISC1 */

/*
 * Macro for accessing the indirect CPR register
 */
#define mtcpr(reg, data)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
#define mfcpr(reg, data)	do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)

#define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */

#define PLLC_SRC_MASK          0x20000000     /* PLL feedback source */

#define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
#define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
#define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */

#define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
#define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
#define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
#define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */

#define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
#define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
#define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
#define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */

#if 0 /* Deprecated */
#define CNTRL_DCR_BASE 0x0f0
#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */

#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */

/* Bit definitions */
#define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
#define PLLMR0_CPU_DIV_BYPASS    0x00000000
#define PLLMR0_CPU_DIV_2         0x00100000
#define PLLMR0_CPU_DIV_3         0x00200000
#define PLLMR0_CPU_DIV_4         0x00300000

#define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
#define PLLMR0_CPU_PLB_DIV_1     0x00000000
#define PLLMR0_CPU_PLB_DIV_2     0x00010000
#define PLLMR0_CPU_PLB_DIV_3     0x00020000
#define PLLMR0_CPU_PLB_DIV_4     0x00030000

#define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
#define PLLMR0_OPB_PLB_DIV_1     0x00000000
#define PLLMR0_OPB_PLB_DIV_2     0x00001000
#define PLLMR0_OPB_PLB_DIV_3     0x00002000
#define PLLMR0_OPB_PLB_DIV_4     0x00003000

#define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
#define PLLMR0_EXB_PLB_DIV_2     0x00000000
#define PLLMR0_EXB_PLB_DIV_3     0x00000100
#define PLLMR0_EXB_PLB_DIV_4     0x00000200
#define PLLMR0_EXB_PLB_DIV_5     0x00000300

#define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
#define PLLMR0_MAL_PLB_DIV_1     0x00000000
#define PLLMR0_MAL_PLB_DIV_2     0x00000010
#define PLLMR0_MAL_PLB_DIV_3     0x00000020
#define PLLMR0_MAL_PLB_DIV_4     0x00000030

#define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
#define PLLMR0_PCI_PLB_DIV_1     0x00000000
#define PLLMR0_PCI_PLB_DIV_2     0x00000001
#define PLLMR0_PCI_PLB_DIV_3     0x00000002
#define PLLMR0_PCI_PLB_DIV_4     0x00000003

#define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
#define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
#define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
#define PLLMR1_FBMUL_DIV_16      0x00000000
#define PLLMR1_FBMUL_DIV_1       0x00100000
#define PLLMR1_FBMUL_DIV_2       0x00200000
#define PLLMR1_FBMUL_DIV_3       0x00300000
#define PLLMR1_FBMUL_DIV_4       0x00400000
#define PLLMR1_FBMUL_DIV_5       0x00500000
#define PLLMR1_FBMUL_DIV_6       0x00600000
#define PLLMR1_FBMUL_DIV_7       0x00700000
#define PLLMR1_FBMUL_DIV_8       0x00800000
#define PLLMR1_FBMUL_DIV_9       0x00900000
#define PLLMR1_FBMUL_DIV_10      0x00A00000
#define PLLMR1_FBMUL_DIV_11      0x00B00000
#define PLLMR1_FBMUL_DIV_12      0x00C00000
#define PLLMR1_FBMUL_DIV_13      0x00D00000
#define PLLMR1_FBMUL_DIV_14      0x00E00000
#define PLLMR1_FBMUL_DIV_15      0x00F00000

#define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
#define PLLMR1_FWDVA_DIV_8       0x00000000
#define PLLMR1_FWDVA_DIV_7       0x00010000
#define PLLMR1_FWDVA_DIV_6       0x00020000
#define PLLMR1_FWDVA_DIV_5       0x00030000
#define PLLMR1_FWDVA_DIV_4       0x00040000
#define PLLMR1_FWDVA_DIV_3       0x00050000
#define PLLMR1_FWDVA_DIV_2       0x00060000
#define PLLMR1_FWDVA_DIV_1       0x00070000
#define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
#define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */

/* Defines for CPC0_EPRCSR register */
#define CPC0_EPRCSR_E0NFE          0x80000000
#define CPC0_EPRCSR_E1NFE          0x40000000
#define CPC0_EPRCSR_E1RPP          0x00000080
#define CPC0_EPRCSR_E0RPP          0x00000040
#define CPC0_EPRCSR_E1ERP          0x00000020
#define CPC0_EPRCSR_E0ERP          0x00000010
#define CPC0_EPRCSR_E1PCI          0x00000002
#define CPC0_EPRCSR_E0PCI          0x00000001

/* Defines for CPC0_BOOR Register */
#define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */

/* Defines for CPC0_PLLMR1 Register fields */
#define PLL_ACTIVE                 0x80000000
#define CPC0_PLLMR1_SSCS           0x80000000
#define PLL_RESET                  0x40000000
#define CPC0_PLLMR1_PLLR           0x40000000
    /* Feedback multiplier */
#define PLL_FBKDIV                 0x00F00000
#define CPC0_PLLMR1_FBDV           0x00F00000
#define PLL_FBKDIV_16              0x00000000
#define PLL_FBKDIV_1               0x00100000
#define PLL_FBKDIV_2               0x00200000
#define PLL_FBKDIV_3               0x00300000
#define PLL_FBKDIV_4               0x00400000
#define PLL_FBKDIV_5               0x00500000
#define PLL_FBKDIV_6               0x00600000
#define PLL_FBKDIV_7               0x00700000