immap_83xx.h

U-boot源码 ARM7启动代码

	u32 mbmr;		/* UPMB Mode Register */
	u32 mcmr;		/* UPMC Mode Register */
	u8 res2[0x8];
	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
	u32 mdr;		/* UPM Data Register */
	u8 res3[0x4];
	u32 lsor;		/* Special Operation Initiation Register */
	u32 lsdmr;		/* SDRAM Mode Register */
	u8 res4[0x8];
	u32 lurt;		/* UPM Refresh Timer */
	u32 lsrt;		/* SDRAM Refresh Timer */
	u8 res5[0x8];
	u32 ltesr;		/* Transfer Error Status Register */
	u32 ltedr;		/* Transfer Error Disable Register */
	u32 lteir;		/* Transfer Error Interrupt Register */
	u32 lteatr;		/* Transfer Error Attributes Register */
	u32 ltear;		/* Transfer Error Address Register */
	u8 res6[0xC];
	u32 lbcr;		/* Configuration Register */
	u32 lcrr;		/* Clock Ratio Register */
	u8 res7[0x8];
	u32 fmr;		/* Flash Mode Register */
	u32 fir;		/* Flash Instruction Register */
	u32 fcr;		/* Flash Command Register */
	u32 fbar;		/* Flash Block Addr Register */
	u32 fpar;		/* Flash Page Addr Register */
	u32 fbcr;		/* Flash Byte Count Register */
	u8 res8[0xF08];
} lbus83xx_t;

/*
 * Serial Peripheral Interface
 */
typedef struct spi83xx {
	u32 mode;		/* mode register */
	u32 event;		/* event register */
	u32 mask;		/* mask register */
	u32 com;		/* command register */
	u8 res0[0x10];
	u32 tx;			/* transmit register */
	u32 rx;			/* receive register */
	u8 res1[0xFD8];
} spi83xx_t;

/*
 * DMA/Messaging Unit
 */
typedef struct dma83xx {
	u32 res0[0xC];		/* 0x0-0x29 reseverd */
	u32 omisr;		/* 0x30 Outbound message interrupt status register */
	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
	u32 res1[0x6];		/* 0x38-0x49 reserved */
	u32 imr0;		/* 0x50 Inbound message register 0 */
	u32 imr1;		/* 0x54 Inbound message register 1 */
	u32 omr0;		/* 0x58 Outbound message register 0 */
	u32 omr1;		/* 0x5C Outbound message register 1 */
	u32 odr;		/* 0x60 Outbound doorbell register */
	u32 res2;		/* 0x64-0x67 reserved */
	u32 idr;		/* 0x68 Inbound doorbell register */
	u32 res3[0x5];		/* 0x6C-0x79 reserved */
	u32 imisr;		/* 0x80 Inbound message interrupt status register */
	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
	u32 res4[0x1E];		/* 0x88-0x99 reserved */
	u32 dmamr0;		/* 0x100 DMA 0 mode register */
	u32 dmasr0;		/* 0x104 DMA 0 status register */
	u32 dmacdar0;		/* 0x108 DMA 0 current descriptor address register */
	u32 res5;		/* 0x10C reserved */
	u32 dmasar0;		/* 0x110 DMA 0 source address register */
	u32 res6;		/* 0x114 reserved */
	u32 dmadar0;		/* 0x118 DMA 0 destination address register */
	u32 res7;		/* 0x11C reserved */
	u32 dmabcr0;		/* 0x120 DMA 0 byte count register */
	u32 dmandar0;		/* 0x124 DMA 0 next descriptor address register */
	u32 res8[0x16];		/* 0x128-0x179 reserved */
	u32 dmamr1;		/* 0x180 DMA 1 mode register */
	u32 dmasr1;		/* 0x184 DMA 1 status register */
	u32 dmacdar1;		/* 0x188 DMA 1 current descriptor address register */
	u32 res9;		/* 0x18C reserved */
	u32 dmasar1;		/* 0x190 DMA 1 source address register */
	u32 res10;		/* 0x194 reserved */
	u32 dmadar1;		/* 0x198 DMA 1 destination address register */
	u32 res11;		/* 0x19C reserved */
	u32 dmabcr1;		/* 0x1A0 DMA 1 byte count register */
	u32 dmandar1;		/* 0x1A4 DMA 1 next descriptor address register */
	u32 res12[0x16];	/* 0x1A8-0x199 reserved */
	u32 dmamr2;		/* 0x200 DMA 2 mode register */
	u32 dmasr2;		/* 0x204 DMA 2 status register */
	u32 dmacdar2;		/* 0x208 DMA 2 current descriptor address register */
	u32 res13;		/* 0x20C reserved */
	u32 dmasar2;		/* 0x210 DMA 2 source address register */
	u32 res14;		/* 0x214 reserved */
	u32 dmadar2;		/* 0x218 DMA 2 destination address register */
	u32 res15;		/* 0x21C reserved */
	u32 dmabcr2;		/* 0x220 DMA 2 byte count register */
	u32 dmandar2;		/* 0x224 DMA 2 next descriptor address register */
	u32 res16[0x16];	/* 0x228-0x279 reserved */
	u32 dmamr3;		/* 0x280 DMA 3 mode register */
	u32 dmasr3;		/* 0x284 DMA 3 status register */
	u32 dmacdar3;		/* 0x288 DMA 3 current descriptor address register */
	u32 res17;		/* 0x28C reserved */
	u32 dmasar3;		/* 0x290 DMA 3 source address register */
	u32 res18;		/* 0x294 reserved */
	u32 dmadar3;		/* 0x298 DMA 3 destination address register */
	u32 res19;		/* 0x29C reserved */
	u32 dmabcr3;		/* 0x2A0 DMA 3 byte count register */
	u32 dmandar3;		/* 0x2A4 DMA 3 next descriptor address register */
	u32 dmagsr;		/* 0x2A8 DMA general status register */
	u32 res20[0x15];	/* 0x2AC-0x2FF reserved */
} dma83xx_t;

/*
 * PCI Software Configuration Registers
 */
typedef struct pciconf83xx {
	u32 config_address;
	u32 config_data;
	u32 int_ack;
	u8 res[116];
} pciconf83xx_t;

/*
 * PCI Outbound Translation Register
 */
typedef struct pci_outbound_window {
	u32 potar;
	u8 res0[4];
	u32 pobar;
	u8 res1[4];
	u32 pocmr;
	u8 res2[4];
} pot83xx_t;

/*
 * Sequencer
 */
typedef struct ios83xx {
	pot83xx_t pot[6];
	u8 res0[0x60];
	u32 pmcr;
	u8 res1[4];
	u32 dtcr;
	u8 res2[4];
} ios83xx_t;

/*
 * PCI Controller Control and Status Registers
 */
typedef struct pcictrl83xx {
	u32 esr;
	u32 ecdr;
	u32 eer;
	u32 eatcr;
	u32 eacr;
	u32 eeacr;
	u32 edlcr;
	u32 edhcr;
	u32 gcr;
	u32 ecr;
	u32 gsr;
	u8 res0[12];
	u32 pitar2;
	u8 res1[4];
	u32 pibar2;
	u32 piebar2;
	u32 piwar2;
	u8 res2[4];
	u32 pitar1;
	u8 res3[4];
	u32 pibar1;
	u32 piebar1;
	u32 piwar1;
	u8 res4[4];
	u32 pitar0;
	u8 res5[4];
	u32 pibar0;
	u8 res6[4];
	u32 piwar0;
	u8 res7[132];
} pcictrl83xx_t;

/*
 * USB
 */
typedef struct usb83xx {
	u8 fixme[0x1000];
} usb83xx_t;

/*
 * TSEC
 */
typedef struct tsec83xx {
	u8 fixme[0x1000];
} tsec83xx_t;

/*
 * Security
 */
typedef struct security83xx {
	u8 fixme[0x10000];
} security83xx_t;

#if defined(CONFIG_MPC834X)
typedef struct immap {
	sysconf83xx_t		sysconf;	/* System configuration */
	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
	rtclk83xx_t		pit;		/* Periodic Interval Timer */
	gtm83xx_t		gtm[2];		/* Global Timers Module */
	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
	reset83xx_t		reset;		/* Reset Module */
	clk83xx_t		clk;		/* System Clock Module */
	pmc83xx_t		pmc;		/* Power Management Control Module */
	gpio83xx_t		gpio[2];	/* General purpose I/O module */
	u8			res0[0x200];
	u8			dll_ddr[0x100];
	u8			dll_lbc[0x100];
	u8			res1[0xE00];
	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
	fsl_i2c_t		i2c[2];		/* I2C Controllers */
	u8			res2[0x1300];
	duart83xx_t		duart[2];	/* DUART */
	u8			res3[0x900];
	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
	u8			res4[0x1000];
	spi83xx_t		spi;		/* Serial Peripheral Interface */
	dma83xx_t		dma;		/* DMA */
	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
	ios83xx_t		ios;		/* Sequencer */
	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
	u8			res5[0x19900];
	usb83xx_t		usb[2];
	tsec83xx_t		tsec[2];
	u8			res6[0xA000];
	security83xx_t		security;
	u8			res7[0xC0000];
} immap_t;

#elif defined(CONFIG_MPC831X)
typedef struct immap {
	sysconf83xx_t		sysconf;	/* System configuration */
	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
	rtclk83xx_t		pit;		/* Periodic Interval Timer */
	gtm83xx_t		gtm[2];		/* Global Timers Module */
	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
	reset83xx_t		reset;		/* Reset Module */
	clk83xx_t		clk;		/* System Clock Module */
	pmc83xx_t		pmc;		/* Power Management Control Module */
	gpio83xx_t		gpio[1];	/* General purpose I/O module */
	u8			res0[0x1300];
	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
	fsl_i2c_t		i2c[2];		/* I2C Controllers */
	u8			res1[0x1300];
	duart83xx_t		duart[2];	/* DUART */
	u8			res2[0x900];
	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
	u8			res3[0x1000];
	spi83xx_t		spi;		/* Serial Peripheral Interface */
	dma83xx_t		dma;		/* DMA */
	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
	u8			res4[0x80];
	ios83xx_t		ios;		/* Sequencer */
	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
	u8			res5[0x1aa00];
	usb83xx_t		usb[1];
	tsec83xx_t		tsec[2];
	u8			res6[0xA000];
	security83xx_t		security;
	u8			res7[0xC0000];
} immap_t;

#elif defined(CONFIG_MPC8360)
typedef struct immap {
	sysconf83xx_t		sysconf;	/* System configuration */
	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
	rtclk83xx_t		pit;		/* Periodic Interval Timer */
	u8			res0[0x200];
	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
	reset83xx_t		reset;		/* Reset Module */
	clk83xx_t		clk;		/* System Clock Module */
	pmc83xx_t		pmc;		/* Power Management Control Module */
	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
	u8			res1[0x300];
	u8			dll_ddr[0x100];
	u8			dll_lbc[0x100];
	u8			res2[0x200];
	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
	u8			res3[0x400];
	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
	fsl_i2c_t		i2c[2];		/* I2C Controllers */
	u8			res4[0x1300];
	duart83xx_t		duart[2];	/* DUART */
	u8			res5[0x900];
	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
	u8			res6[0x2000];
	dma83xx_t		dma;		/* DMA */
	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
	u8			res7[128];
	ios83xx_t		ios;		/* Sequencer (IOS) */
	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
	u8			res8[0x4A00];
	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
	u8			res9[0x22000];
	security83xx_t		security;
	u8			res10[0xC0000];
	u8			qe[0x100000];	/* QE block */
} immap_t;

#elif defined(CONFIG_MPC832X)
typedef struct immap {
	sysconf83xx_t		sysconf;	/* System configuration */
	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
	rtclk83xx_t		pit;		/* Periodic Interval Timer */
	gtm83xx_t		gtm[2];		/* Global Timers Module */
	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
	reset83xx_t		reset;		/* Reset Module */
	clk83xx_t		clk;		/* System Clock Module */
	pmc83xx_t		pmc;		/* Power Management Control Module */
	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
	u8			res0[0x300];
	u8			dll_ddr[0x100];
	u8			dll_lbc[0x100];
	u8			res1[0x200];
	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
	u8			res2[0x800];
	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
	fsl_i2c_t		i2c[2];		/* I2C Controllers */
	u8			res3[0x1300];
	duart83xx_t		duart[2];	/* DUART */
	u8			res4[0x900];
	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
	u8			res5[0x2000];
	dma83xx_t		dma;		/* DMA */
	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
	u8			res6[128];
	ios83xx_t		ios;		/* Sequencer (IOS) */
	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
	u8			res7[0x27A00];
	security83xx_t		security;
	u8			res8[0xC0000];
	u8			qe[0x100000];	/* QE block */
} immap_t;
#endif

#endif				/* __IMMAP_83xx__ */