mmu.h

U-boot源码 ARM7启动代码

/*
 * TLB entries are defined by a "high" tag portion and a "low" data
 * portion.  On all architectures, the data portion is 32-bits.
 *
 * TLB entries are managed entirely under software control by reading,
 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 * instructions.
 */

/*
 * e500 support
 */

#define MAS0_TLBSEL     0x10000000
#define MAS0_ESEL       0x000F0000
#define MAS0_NV         0x00000001

#define MAS1_VALID      0x80000000
#define MAS1_IPROT      0x40000000
#define MAS1_TID        0x00FF0000
#define MAS1_TS         0x00001000
#define MAS1_TSIZE   	0x00000F00

#define MAS2_EPN        0xFFFFF000
#define MAS2_SHAREN     0x00000200
#define MAS2_X0         0x00000040
#define MAS2_X1         0x00000020
#define MAS2_W          0x00000010
#define MAS2_I          0x00000008
#define MAS2_M          0x00000004
#define MAS2_G          0x00000002
#define MAS2_E          0x00000001

#define MAS3_RPN        0xFFFFF000
#define MAS3_U0         0x00000200
#define MAS3_U1         0x00000100
#define MAS3_U2         0x00000080
#define MAS3_U3         0x00000040
#define MAS3_UX         0x00000020
#define MAS3_SX         0x00000010
#define MAS3_UW         0x00000008
#define MAS3_SW         0x00000004
#define MAS3_UR         0x00000002
#define MAS3_SR         0x00000001

#define MAS4_TLBSELD    0x10000000
#define MAS4_TIDDSEL    0x00030000
#define MAS4_DSHAREN    0x00001000
#define MAS4_TSIZED(x)  (x << 8)
#define MAS4_X0D        0x00000040
#define MAS4_X1D        0x00000020
#define MAS4_WD         0x00000010
#define MAS4_ID         0x00000008
#define MAS4_MD         0x00000004
#define MAS4_GD         0x00000002
#define MAS4_ED         0x00000001

#define MAS6_SPID       0x00FF0000
#define MAS6_SAS        0x00000001

#define BOOKE_PAGESZ_1K         0
#define BOOKE_PAGESZ_4K         1
#define BOOKE_PAGESZ_16K        2
#define BOOKE_PAGESZ_64K        3
#define BOOKE_PAGESZ_256K       4
#define BOOKE_PAGESZ_1M         5
#define BOOKE_PAGESZ_4M         6
#define BOOKE_PAGESZ_16M        7
#define BOOKE_PAGESZ_64M        8
#define BOOKE_PAGESZ_256M       9
#define BOOKE_PAGESZ_1G		10
#define BOOKE_PAGESZ_4G		11

#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR	0x00FFFFFF
#define LAWAR_TRGT_IF		0x01F00000
#else
#define LAWBAR_BASE_ADDR	0x000FFFFF
#define LAWAR_TRGT_IF		0x00F00000
#endif
#define LAWAR_EN		0x80000000
#define LAWAR_SIZE		0x0000003F

#define LAWAR_TRGT_IF_PCI	0x00000000
#define LAWAR_TRGT_IF_PCI1	0x00000000
#define LAWAR_TRGT_IF_PCIX	0x00000000
#define LAWAR_TRGT_IF_PCI2	0x00100000
#define LAWAR_TRGT_IF_PEX	0x00200000
#define LAWAR_TRGT_IF_LBC	0x00400000
#define LAWAR_TRGT_IF_CCSR	0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO	0x00c00000
#define LAWAR_TRGT_IF_DDR	0x00f00000
#define LAWAR_TRGT_IF_DDR1	0x00f00000
#define LAWAR_TRGT_IF_DDR2	0x01600000

#define LAWAR_SIZE_BASE		0xa
#define LAWAR_SIZE_4K		(LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_8K		(LAWAR_SIZE_BASE+2)
#define LAWAR_SIZE_16K		(LAWAR_SIZE_BASE+3)
#define LAWAR_SIZE_32K		(LAWAR_SIZE_BASE+4)
#define LAWAR_SIZE_64K		(LAWAR_SIZE_BASE+5)
#define LAWAR_SIZE_128K		(LAWAR_SIZE_BASE+6)
#define LAWAR_SIZE_256K		(LAWAR_SIZE_BASE+7)
#define LAWAR_SIZE_512K		(LAWAR_SIZE_BASE+8)
#define LAWAR_SIZE_1M		(LAWAR_SIZE_BASE+9)
#define LAWAR_SIZE_2M		(LAWAR_SIZE_BASE+10)
#define LAWAR_SIZE_4M		(LAWAR_SIZE_BASE+11)
#define LAWAR_SIZE_8M		(LAWAR_SIZE_BASE+12)
#define LAWAR_SIZE_16M		(LAWAR_SIZE_BASE+13)
#define LAWAR_SIZE_32M		(LAWAR_SIZE_BASE+14)
#define LAWAR_SIZE_64M		(LAWAR_SIZE_BASE+15)
#define LAWAR_SIZE_128M		(LAWAR_SIZE_BASE+16)
#define LAWAR_SIZE_256M		(LAWAR_SIZE_BASE+17)
#define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
#define LAWAR_SIZE_4G		(LAWAR_SIZE_BASE+21)
#define LAWAR_SIZE_8G		(LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)

#ifdef CONFIG_440
/* General */
#define TLB_VALID   0x00000200

/* Supported page sizes */

#define SZ_1K	0x00000000
#define SZ_4K	0x00000010
#define SZ_16K	0x00000020
#define SZ_64K	0x00000030
#define SZ_256K	0x00000040
#define SZ_1M	0x00000050
#define SZ_16M	0x00000070
#define SZ_256M	0x00000090

/* Storage attributes */
#define SA_W	0x00000800	/* Write-through */
#define SA_I	0x00000400	/* Caching inhibited */
#define SA_M	0x00000200	/* Memory coherence */
#define SA_G	0x00000100	/* Guarded */
#define SA_E	0x00000080	/* Endian */

/* Access control */
#define AC_X	0x00000024	/* Execute */
#define AC_W	0x00000012	/* Write */
#define AC_R	0x00000009	/* Read */

/* Some handy macros */

#define EPN(e)		((e) & 0xfffffc00)
#define TLB0(epn,sz)	((EPN((epn)) | (sz) | TLB_VALID ))
#define TLB1(rpn,erpn)	(((rpn) & 0xfffffc00) | (erpn))
#define TLB2(a)		((a) & 0x00000fbf)

#define tlbtab_start\
	mflr	r1	;\
	bl	0f	;

#define tlbtab_end\
	.long 0, 0, 0	;\
0:	mflr	r0	;\
	mtlr	r1	;\
	blr		;

#define tlbentry(epn,sz,rpn,erpn,attr)\
	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)

/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK 0xF0000000
#define TLB_16MB_ALIGN_MASK  0xFF000000
#define TLB_1MB_ALIGN_MASK   0xFFF00000
#define TLB_256KB_ALIGN_MASK 0xFFFC0000
#define TLB_64KB_ALIGN_MASK  0xFFFF0000
#define TLB_16KB_ALIGN_MASK  0xFFFFC000
#define TLB_4KB_ALIGN_MASK   0xFFFFF000
#define TLB_1KB_ALIGN_MASK   0xFFFFFC00
#define TLB_256MB_SIZE       0x10000000
#define TLB_16MB_SIZE        0x01000000
#define TLB_1MB_SIZE         0x00100000
#define TLB_256KB_SIZE       0x00040000
#define TLB_64KB_SIZE        0x00010000
#define TLB_16KB_SIZE        0x00004000
#define TLB_4KB_SIZE         0x00001000
#define TLB_1KB_SIZE         0x00000400

#define TLB_WORD0_EPN_MASK   0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK     0x00000200
#define TLB_WORD0_V_ENABLE   0x00000200
#define TLB_WORD0_V_DISABLE  0x00000000
#define TLB_WORD0_TS_MASK    0x00000100
#define TLB_WORD0_TS_1       0x00000100
#define TLB_WORD0_TS_0       0x00000000
#define TLB_WORD0_SIZE_MASK  0x000000F0
#define TLB_WORD0_SIZE_1KB   0x00000000
#define TLB_WORD0_SIZE_4KB   0x00000010
#define TLB_WORD0_SIZE_16KB  0x00000020
#define TLB_WORD0_SIZE_64KB  0x00000030
#define TLB_WORD0_SIZE_256KB 0x00000040
#define TLB_WORD0_SIZE_1MB   0x00000050
#define TLB_WORD0_SIZE_16MB  0x00000070
#define TLB_WORD0_SIZE_256MB 0x00000090
#define TLB_WORD0_TPAR_MASK  0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)

#define TLB_WORD1_RPN_MASK   0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK  0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0     0x00000000
#define TLB_WORD1_PAR1_1     0x00000100
#define TLB_WORD1_PAR1_2     0x00000200
#define TLB_WORD1_PAR1_3     0x00000300
#define TLB_WORD1_ERPN_MASK  0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)

#define TLB_WORD2_PAR2_MASK  0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0     0x00000000
#define TLB_WORD2_PAR2_1     0x40000000
#define TLB_WORD2_PAR2_2     0x80000000
#define TLB_WORD2_PAR2_3     0xC0000000
#define TLB_WORD2_U0_MASK    0x00008000
#define TLB_WORD2_U0_ENABLE  0x00008000
#define TLB_WORD2_U0_DISABLE 0x00000000
#define TLB_WORD2_U1_MASK    0x00004000
#define TLB_WORD2_U1_ENABLE  0x00004000
#define TLB_WORD2_U1_DISABLE 0x00000000
#define TLB_WORD2_U2_MASK    0x00002000
#define TLB_WORD2_U2_ENABLE  0x00002000
#define TLB_WORD2_U2_DISABLE 0x00000000
#define TLB_WORD2_U3_MASK    0x00001000
#define TLB_WORD2_U3_ENABLE  0x00001000
#define TLB_WORD2_U3_DISABLE 0x00000000
#define TLB_WORD2_W_MASK     0x00000800
#define TLB_WORD2_W_ENABLE   0x00000800
#define TLB_WORD2_W_DISABLE  0x00000000
#define TLB_WORD2_I_MASK     0x00000400
#define TLB_WORD2_I_ENABLE   0x00000400
#define TLB_WORD2_I_DISABLE  0x00000000
#define TLB_WORD2_M_MASK     0x00000200
#define TLB_WORD2_M_ENABLE   0x00000200
#define TLB_WORD2_M_DISABLE  0x00000000
#define TLB_WORD2_G_MASK     0x00000100
#define TLB_WORD2_G_ENABLE   0x00000100
#define TLB_WORD2_G_DISABLE  0x00000000
#define TLB_WORD2_E_MASK     0x00000080
#define TLB_WORD2_E_ENABLE   0x00000080
#define TLB_WORD2_E_DISABLE  0x00000000
#define TLB_WORD2_UX_MASK    0x00000020
#define TLB_WORD2_UX_ENABLE  0x00000020
#define TLB_WORD2_UX_DISABLE 0x00000000
#define TLB_WORD2_UW_MASK    0x00000010
#define TLB_WORD2_UW_ENABLE  0x00000010
#define TLB_WORD2_UW_DISABLE 0x00000000
#define TLB_WORD2_UR_MASK    0x00000008
#define TLB_WORD2_UR_ENABLE  0x00000008
#define TLB_WORD2_UR_DISABLE 0x00000000
#define TLB_WORD2_SX_MASK    0x00000004
#define TLB_WORD2_SX_ENABLE  0x00000004
#define TLB_WORD2_SX_DISABLE 0x00000000
#define TLB_WORD2_SW_MASK    0x00000002
#define TLB_WORD2_SW_ENABLE  0x00000002
#define TLB_WORD2_SW_DISABLE 0x00000000
#define TLB_WORD2_SR_MASK    0x00000001
#define TLB_WORD2_SR_ENABLE  0x00000001
#define TLB_WORD2_SR_DISABLE 0x00000000

/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define DCCCI(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(454<<1)

#define ICCCI(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(966<<1)

#define DCREAD(rt,ra,rb)		.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)

#define ICREAD(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(998<<1)

#define TLBSX(rt,ra,rb)			.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)

#define TLBWE(rs,ra,ws)			.long 0x7c000000|\
					(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)

#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)

#define TLBSXDOT(rt,ra,rb)		.long 0x7c000001|\
					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)

#define MSYNC				.long 0x7c000000|\
					(598<<1)

#define MBAR_INST 				.long 0x7c000000|\
					(854<<1)

#ifndef __ASSEMBLY__
/* Prototypes */
void mttlb1(unsigned long index, unsigned long value);
void mttlb2(unsigned long index, unsigned long value);
void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);

void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */

#endif /* CONFIG_440 */
#endif /* _PPC_MMU_H_ */