mpc83xx.h

U-boot源码 ARM7启动代码

#define BR_MS_GPCM			0x00000000	/* GPCM */
#define BR_MS_FCM			0x00000020	/* FCM */
#define BR_MS_SDRAM			0x00000060	/* SDRAM */
#define BR_MS_UPMA			0x00000080	/* UPMA */
#define BR_MS_UPMB			0x000000A0	/* UPMB */
#define BR_MS_UPMC			0x000000C0	/* UPMC */
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
#define BR_ATOM				0x0000000C
#define BR_ATOM_SHIFT			2
#endif
#define BR_V				0x00000001
#define BR_V_SHIFT			0

#if defined(CONFIG_MPC834X)
#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#elif defined(CONFIG_MPC8360)
#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif

/* OR - Option Registers
 */
#define OR0				0x5004		/* Register offset to immr */
#define OR1				0x500C
#define OR2				0x5014
#define OR3				0x501C
#define OR4				0x5024
#define OR5				0x502C
#define OR6				0x5034
#define OR7				0x503C

#define OR_GPCM_AM			0xFFFF8000
#define OR_GPCM_AM_SHIFT		15
#define OR_GPCM_BCTLD			0x00001000
#define OR_GPCM_BCTLD_SHIFT		12
#define OR_GPCM_CSNT			0x00000800
#define OR_GPCM_CSNT_SHIFT		11
#define OR_GPCM_ACS			0x00000600
#define OR_GPCM_ACS_SHIFT		9
#define OR_GPCM_ACS_0b10		0x00000400
#define OR_GPCM_ACS_0b11		0x00000600
#define OR_GPCM_XACS			0x00000100
#define OR_GPCM_XACS_SHIFT		8
#define OR_GPCM_SCY			0x000000F0
#define OR_GPCM_SCY_SHIFT		4
#define OR_GPCM_SCY_1			0x00000010
#define OR_GPCM_SCY_2			0x00000020
#define OR_GPCM_SCY_3			0x00000030
#define OR_GPCM_SCY_4			0x00000040
#define OR_GPCM_SCY_5			0x00000050
#define OR_GPCM_SCY_6			0x00000060
#define OR_GPCM_SCY_7			0x00000070
#define OR_GPCM_SCY_8			0x00000080
#define OR_GPCM_SCY_9			0x00000090
#define OR_GPCM_SCY_10			0x000000a0
#define OR_GPCM_SCY_11			0x000000b0
#define OR_GPCM_SCY_12			0x000000c0
#define OR_GPCM_SCY_13			0x000000d0
#define OR_GPCM_SCY_14			0x000000e0
#define OR_GPCM_SCY_15			0x000000f0
#define OR_GPCM_SETA			0x00000008
#define OR_GPCM_SETA_SHIFT		3
#define OR_GPCM_TRLX			0x00000004
#define OR_GPCM_TRLX_SHIFT		2
#define OR_GPCM_EHTR			0x00000002
#define OR_GPCM_EHTR_SHIFT		1
#define OR_GPCM_EAD			0x00000001
#define OR_GPCM_EAD_SHIFT		0

#define OR_FCM_AM			0xFFFF8000
#define OR_FCM_AM_SHIFT				15
#define OR_FCM_BCTLD			0x00001000
#define OR_FCM_BCTLD_SHIFT			12
#define OR_FCM_PGS			0x00000400
#define OR_FCM_PGS_SHIFT			10
#define OR_FCM_CSCT			0x00000200
#define OR_FCM_CSCT_SHIFT			 9
#define OR_FCM_CST			0x00000100
#define OR_FCM_CST_SHIFT			 8
#define OR_FCM_CHT			0x00000080
#define OR_FCM_CHT_SHIFT			 7
#define OR_FCM_SCY			0x00000070
#define OR_FCM_SCY_SHIFT			 4
#define OR_FCM_SCY_1			0x00000010
#define OR_FCM_SCY_2			0x00000020
#define OR_FCM_SCY_3			0x00000030
#define OR_FCM_SCY_4			0x00000040
#define OR_FCM_SCY_5			0x00000050
#define OR_FCM_SCY_6			0x00000060
#define OR_FCM_SCY_7			0x00000070
#define OR_FCM_RST			0x00000008
#define OR_FCM_RST_SHIFT			 3
#define OR_FCM_TRLX			0x00000004
#define OR_FCM_TRLX_SHIFT			 2
#define OR_FCM_EHTR			0x00000002
#define OR_FCM_EHTR_SHIFT			 1

#define OR_UPM_AM			0xFFFF8000
#define OR_UPM_AM_SHIFT			15
#define OR_UPM_XAM			0x00006000
#define OR_UPM_XAM_SHIFT		13
#define OR_UPM_BCTLD			0x00001000
#define OR_UPM_BCTLD_SHIFT		12
#define OR_UPM_BI			0x00000100
#define OR_UPM_BI_SHIFT			8
#define OR_UPM_TRLX			0x00000004
#define OR_UPM_TRLX_SHIFT		2
#define OR_UPM_EHTR			0x00000002
#define OR_UPM_EHTR_SHIFT		1
#define OR_UPM_EAD			0x00000001
#define OR_UPM_EAD_SHIFT		0

#define OR_SDRAM_AM			0xFFFF8000
#define OR_SDRAM_AM_SHIFT		15
#define OR_SDRAM_XAM			0x00006000
#define OR_SDRAM_XAM_SHIFT		13
#define OR_SDRAM_COLS			0x00001C00
#define OR_SDRAM_COLS_SHIFT		10
#define OR_SDRAM_ROWS			0x000001C0
#define OR_SDRAM_ROWS_SHIFT		6
#define OR_SDRAM_PMSEL			0x00000020
#define OR_SDRAM_PMSEL_SHIFT		5
#define OR_SDRAM_EAD			0x00000001
#define OR_SDRAM_EAD_SHIFT		0

#define OR_AM_32KB			0xFFFF8000
#define OR_AM_64KB			0xFFFF0000
#define OR_AM_128KB			0xFFFE0000
#define OR_AM_256KB			0xFFFC0000
#define OR_AM_512KB			0xFFF80000
#define OR_AM_1MB			0xFFF00000
#define OR_AM_2MB			0xFFE00000
#define OR_AM_4MB			0xFFC00000
#define OR_AM_8MB			0xFF800000
#define OR_AM_16MB			0xFF000000
#define OR_AM_32MB			0xFE000000
#define OR_AM_64MB			0xFC000000
#define OR_AM_128MB			0xF8000000
#define OR_AM_256MB			0xF0000000
#define OR_AM_512MB			0xE0000000
#define OR_AM_1GB			0xC0000000
#define OR_AM_2GB			0x80000000
#define OR_AM_4GB			0x00000000

#define LBLAWAR_EN			0x80000000
#define LBLAWAR_4KB			0x0000000B
#define LBLAWAR_8KB			0x0000000C
#define LBLAWAR_16KB			0x0000000D
#define LBLAWAR_32KB			0x0000000E
#define LBLAWAR_64KB			0x0000000F
#define LBLAWAR_128KB			0x00000010
#define LBLAWAR_256KB			0x00000011
#define LBLAWAR_512KB			0x00000012
#define LBLAWAR_1MB			0x00000013
#define LBLAWAR_2MB			0x00000014
#define LBLAWAR_4MB			0x00000015
#define LBLAWAR_8MB			0x00000016
#define LBLAWAR_16MB			0x00000017
#define LBLAWAR_32MB			0x00000018
#define LBLAWAR_64MB			0x00000019
#define LBLAWAR_128MB			0x0000001A
#define LBLAWAR_256MB			0x0000001B
#define LBLAWAR_512MB			0x0000001C
#define LBLAWAR_1GB			0x0000001D
#define LBLAWAR_2GB			0x0000001E

/* LBCR - Local Bus Configuration Register
 */
#define LBCR_LDIS			0x80000000
#define LBCR_LDIS_SHIFT			31
#define LBCR_BCTLC			0x00C00000
#define LBCR_BCTLC_SHIFT		22
#define LBCR_LPBSE			0x00020000
#define LBCR_LPBSE_SHIFT		17
#define LBCR_EPAR			0x00010000
#define LBCR_EPAR_SHIFT			16
#define LBCR_BMT			0x0000FF00
#define LBCR_BMT_SHIFT			8

/* LCRR - Clock Ratio Register
 */
#define LCRR_DBYP			0x80000000
#define LCRR_DBYP_SHIFT			31
#define LCRR_BUFCMDC			0x30000000
#define LCRR_BUFCMDC_SHIFT		28
#define LCRR_BUFCMDC_1			0x10000000
#define LCRR_BUFCMDC_2			0x20000000
#define LCRR_BUFCMDC_3			0x30000000
#define LCRR_BUFCMDC_4			0x00000000
#define LCRR_ECL			0x03000000
#define LCRR_ECL_SHIFT			24
#define LCRR_ECL_4			0x00000000
#define LCRR_ECL_5			0x01000000
#define LCRR_ECL_6			0x02000000
#define LCRR_ECL_7			0x03000000
#define LCRR_EADC			0x00030000
#define LCRR_EADC_SHIFT			16
#define LCRR_EADC_1			0x00010000
#define LCRR_EADC_2			0x00020000
#define LCRR_EADC_3			0x00030000
#define LCRR_EADC_4			0x00000000
#define LCRR_CLKDIV			0x0000000F
#define LCRR_CLKDIV_SHIFT		0
#define LCRR_CLKDIV_2			0x00000002
#define LCRR_CLKDIV_4			0x00000004
#define LCRR_CLKDIV_8			0x00000008

/* DMAMR - DMA Mode Register
 */
#define DMA_CHANNEL_START			0x00000001	/* Bit - DMAMRn CS */
#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	0x00000004	/* Bit - DMAMRn CTM */
#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	0x00001000	/* Bit - DMAMRn SAHE */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	0x00000000	/* 2Bit- DMAMRn SAHTS 1byte */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	0x00004000	/* 2Bit- DMAMRn SAHTS 2bytes */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	0x00008000	/* 2Bit- DMAMRn SAHTS 4bytes */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	0x0000c000	/* 2Bit- DMAMRn SAHTS 8bytes */
#define DMA_CHANNEL_SNOOP			0x00010000	/* Bit - DMAMRn DMSEN */

/* DMASR - DMA Status Register
 */
#define DMA_CHANNEL_BUSY			0x00000004	/* Bit - DMASRn CB */
#define DMA_CHANNEL_TRANSFER_ERROR		0x00000080	/* Bit - DMASRn TE */

/* CONFIG_ADDRESS - PCI Config Address Register
 */
#define PCI_CONFIG_ADDRESS_EN		0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc

/* POTAR - PCI Outbound Translation Address Register
 */
#define POTAR_TA_MASK			0x000fffff

/* POBAR - PCI Outbound Base Address Register
 */
#define POBAR_BA_MASK			0x000fffff

/* POCMR - PCI Outbound Comparision Mask Register
 */
#define POCMR_EN			0x80000000
#define POCMR_IO			0x40000000	/* 0-memory space 1-I/O space */
#define POCMR_SE			0x20000000	/* streaming enable */
#define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
#define POCMR_CM_MASK			0x000fffff
#define POCMR_CM_4G			0x00000000
#define POCMR_CM_2G			0x00080000
#define POCMR_CM_1G			0x000C0000
#define POCMR_CM_512M			0x000E0000
#define POCMR_CM_256M			0x000F0000
#define POCMR_CM_128M			0x000F8000
#define POCMR_CM_64M			0x000FC000
#define POCMR_CM_32M			0x000FE000
#define POCMR_CM_16M			0x000FF000
#define POCMR_CM_8M			0x000FF800
#define POCMR_CM_4M			0x000FFC00
#define POCMR_CM_2M			0x000FFE00
#define POCMR_CM_1M			0x000FFF00
#define POCMR_CM_512K			0x000FFF80
#define POCMR_CM_256K			0x000FFFC0
#define POCMR_CM_128K			0x000FFFE0
#define POCMR_CM_64K			0x000FFFF0
#define POCMR_CM_32K			0x000FFFF8
#define POCMR_CM_16K			0x000FFFFC
#define POCMR_CM_8K			0x000FFFFE
#define POCMR_CM_4K			0x000FFFFF

/* PITAR - PCI Inbound Translation Address Register
 */
#define PITAR_TA_MASK			0x000fffff

/* PIBAR - PCI Inbound Base/Extended Address Register
 */
#define PIBAR_MASK			0xffffffff
#define PIEBAR_EBA_MASK			0x000fffff

/* PIWAR - PCI Inbound Windows Attributes Register
 */
#define PIWAR_EN			0x80000000
#define PIWAR_PF			0x20000000
#define PIWAR_RTT_MASK			0x000f0000
#define PIWAR_RTT_NO_SNOOP		0x00040000
#define PIWAR_RTT_SNOOP			0x00050000
#define PIWAR_WTT_MASK			0x0000f000
#define PIWAR_WTT_NO_SNOOP		0x00004000
#define PIWAR_WTT_SNOOP			0x00005000
#define PIWAR_IWS_MASK			0x0000003F
#define PIWAR_IWS_4K			0x0000000B
#define PIWAR_IWS_8K			0x0000000C
#define PIWAR_IWS_16K			0x0000000D
#define PIWAR_IWS_32K			0x0000000E
#define PIWAR_IWS_64K			0x0000000F
#define PIWAR_IWS_128K			0x00000010
#define PIWAR_IWS_256K			0x00000011
#define PIWAR_IWS_512K			0x00000012
#define PIWAR_IWS_1M			0x00000013
#define PIWAR_IWS_2M			0x00000014
#define PIWAR_IWS_4M			0x00000015
#define PIWAR_IWS_8M			0x00000016
#define PIWAR_IWS_16M			0x00000017
#define PIWAR_IWS_32M			0x00000018
#define PIWAR_IWS_64M			0x00000019
#define PIWAR_IWS_128M			0x0000001A
#define PIWAR_IWS_256M			0x0000001B
#define PIWAR_IWS_512M			0x0000001C
#define PIWAR_IWS_1G			0x0000001D
#define PIWAR_IWS_2G			0x0000001E

/* PMCCR1 - PCI Configuration Register 1
 */
#define PMCCR1_POWER_OFF		0x00000020

/* FMR - Flash Mode Register
 */
#define FMR_CWTO		0x0000F000
#define FMR_CWTO_SHIFT		12
#define FMR_BOOT		0x00000800
#define FMR_ECCM		0x00000100
#define FMR_AL			0x00000030
#define FMR_AL_SHIFT		4
#define FMR_OP			0x00000003
#define FMR_OP_SHIFT		0

/* FIR - Flash Instruction Register
 */
#define FIR_OP0			0xF0000000
#define FIR_OP0_SHIFT		28
#define FIR_OP1			0x0F000000
#define FIR_OP1_SHIFT		24
#define FIR_OP2			0x00F00000
#define FIR_OP2_SHIFT		20
#define FIR_OP3			0x000F0000
#define FIR_OP3_SHIFT		16
#define FIR_OP4			0x0000F000
#define FIR_OP4_SHIFT		12
#define FIR_OP5			0x00000F00
#define FIR_OP5_SHIFT		8
#define FIR_OP6			0x000000F0
#define FIR_OP6_SHIFT		4
#define FIR_OP7			0x0000000F
#define FIR_OP7_SHIFT		0
#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
#define FIR_OP_CA		0x1 /* Issue current column address */
#define FIR_OP_PA		0x2 /* Issue current block+page address */
#define FIR_OP_UA		0x3 /* Issue user defined address */
#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */

/* FCR - Flash Command Register
 */
#define FCR_CMD0		0xFF000000
#define FCR_CMD0_SHIFT		24
#define FCR_CMD1		0x00FF0000
#define FCR_CMD1_SHIFT		16
#define FCR_CMD2		0x0000FF00
#define FCR_CMD2_SHIFT		8
#define FCR_CMD3		0x000000FF
#define FCR_CMD3_SHIFT		0

/* FBAR - Flash Block Address Register
 */
#define FBAR_BLK		0x00FFFFFF

/* FPAR - Flash Page Address Register
 */
#define FPAR_SP_PI		0x00007C00
#define FPAR_SP_PI_SHIFT	10
#define FPAR_SP_MS		0x00000200
#define FPAR_SP_CI		0x000001FF
#define FPAR_SP_CI_SHIFT	0
#define FPAR_LP_PI		0x0003F000
#define FPAR_LP_PI_SHIFT	12
#define FPAR_LP_MS		0x00000800
#define FPAR_LP_CI		0x000007FF
#define FPAR_LP_CI_SHIFT	0

/* LTESR - Transfer Error Status Register
 */
#define LTESR_BM		0x80000000
#define LTESR_FCT		0x40000000
#define LTESR_PAR		0x20000000
#define LTESR_WP		0x04000000
#define LTESR_ATMW		0x00800000
#define LTESR_ATMR		0x00400000
#define LTESR_CS		0x00080000
#define LTESR_CC		0x00000001

/* DDR Control Driver Register
 */
#define DDRCDR_EN		0x40000000
#define DDRCDR_PZ		0x3C000000
#define DDRCDR_PZ_MAXZ		0x00000000
#define DDRCDR_PZ_HIZ		0x20000000
#define DDRCDR_PZ_NOMZ		0x30000000
#define DDRCDR_PZ_LOZ		0x38000000
#define DDRCDR_PZ_MINZ		0x3C000000
#define DDRCDR_NZ		0x3C000000
#define DDRCDR_NZ_MAXZ		0x00000000
#define DDRCDR_NZ_HIZ		0x02000000
#define DDRCDR_NZ_NOMZ		0x03000000
#define DDRCDR_NZ_LOZ		0x03800000
#define DDRCDR_NZ_MINZ		0x03C00000
#define DDRCDR_ODT		0x00080000
#define DDRCDR_DDR_CFG		0x00040000
#define DDRCDR_M_ODR		0x00000002
#define DDRCDR_Q_DRN		0x00000001

#ifndef __ASSEMBLY__
struct pci_region;
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
#endif

#endif	/* __MPC83XX_H__ */