mpc83xx.h

U-boot源码 ARM7启动代码

/*
 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#ifndef __MPC83XX_H__
#define __MPC83XX_H__

#include <config.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif

/* MPC83xx cpu provide RCR register to do reset thing specially
 */
#define MPC83xx_RESET

/* System reset offset (PowerPC standard)
 */
#define EXC_OFF_SYS_RESET		0x0100
#define	_START_OFFSET			EXC_OFF_SYS_RESET

/* IMMRBAR - Internal Memory Register Base Address
 */
#define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
#define IMMRBAR				0x0000		/* Register offset to immr */
#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)

/* LAWBAR - Local Access Window Base Address Register
 */
#define LBLAWBAR0			0x0020		/* Register offset to immr */
#define LBLAWAR0			0x0024
#define LBLAWBAR1			0x0028
#define LBLAWAR1			0x002C
#define LBLAWBAR2			0x0030
#define LBLAWAR2			0x0034
#define LBLAWBAR3			0x0038
#define LBLAWAR3			0x003C
#define LAWBAR_BAR			0xFFFFF000	/* Base address mask */

/* SPRIDR - System Part and Revision ID Register
 */
#define SPRIDR_PARTID			0xFFFF0000	/* Part Identification */
#define SPRIDR_REVID			0x0000FFFF	/* Revision Identification */

#define SPR_8349E_REV10			0x80300100
#define SPR_8349_REV10			0x80310100
#define SPR_8347E_REV10_TBGA		0x80320100
#define SPR_8347_REV10_TBGA		0x80330100
#define SPR_8347E_REV10_PBGA		0x80340100
#define SPR_8347_REV10_PBGA		0x80350100
#define SPR_8343E_REV10			0x80360100
#define SPR_8343_REV10			0x80370100

#define SPR_8349E_REV11			0x80300101
#define SPR_8349_REV11			0x80310101
#define SPR_8347E_REV11_TBGA		0x80320101
#define SPR_8347_REV11_TBGA		0x80330101
#define SPR_8347E_REV11_PBGA		0x80340101
#define SPR_8347_REV11_PBGA		0x80350101
#define SPR_8343E_REV11			0x80360101
#define SPR_8343_REV11			0x80370101

#define SPR_8349E_REV31			0x80300300
#define SPR_8349_REV31			0x80310300
#define SPR_8347E_REV31_TBGA		0x80320300
#define SPR_8347_REV31_TBGA		0x80330300
#define SPR_8347E_REV31_PBGA		0x80340300
#define SPR_8347_REV31_PBGA		0x80350300
#define SPR_8343E_REV31			0x80360300
#define SPR_8343_REV31			0x80370300

#define SPR_8360E_REV10			0x80480010
#define SPR_8360_REV10			0x80490010
#define SPR_8360E_REV11			0x80480011
#define SPR_8360_REV11			0x80490011
#define SPR_8360E_REV12			0x80480012
#define SPR_8360_REV12			0x80490012
#define SPR_8360E_REV20			0x80480020
#define SPR_8360_REV20			0x80490020
#define SPR_8360E_REV21			0x80480021
#define SPR_8360_REV21			0x80490021

#define SPR_8323E_REV10			0x80620010
#define SPR_8323_REV10			0x80630010
#define SPR_8321E_REV10			0x80660010
#define SPR_8321_REV10			0x80670010
#define SPR_8323E_REV11			0x80620011
#define SPR_8323_REV11			0x80630011
#define SPR_8321E_REV11			0x80660011
#define SPR_8321_REV11			0x80670011

#define SPR_8311_REV10			0x80B30010
#define SPR_8311E_REV10			0x80B20010
#define SPR_8313_REV10			0x80B10010
#define SPR_8313E_REV10			0x80B00010

/* SPCR - System Priority Configuration Register
 */
#define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
#define SPCR_PCIHPE_SHIFT		(31-3)
#define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
#define SPCR_PCIPR_SHIFT		(31-7)
#define SPCR_OPT			0x00800000	/* Optimize */
#define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
#define SPCR_TBEN_SHIFT			(31-9)
#define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
#define SPCR_COREPR_SHIFT		(31-11)

#if defined(CONFIG_MPC834X)
/* SPCR bits - MPC8349 specific */
#define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
#define SPCR_TSEC1DP_SHIFT		(31-19)
#define SPCR_TSEC1BDP			0x00000C00	/* TSEC1 buffer descriptor priority */
#define SPCR_TSEC1BDP_SHIFT		(31-21)
#define SPCR_TSEC1EP			0x00000300	/* TSEC1 emergency priority */
#define SPCR_TSEC1EP_SHIFT		(31-23)
#define SPCR_TSEC2DP			0x00000030	/* TSEC2 data priority */
#define SPCR_TSEC2DP_SHIFT		(31-27)
#define SPCR_TSEC2BDP			0x0000000C	/* TSEC2 buffer descriptor priority */
#define SPCR_TSEC2BDP_SHIFT		(31-29)
#define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
#define SPCR_TSEC2EP_SHIFT		(31-31)

#elif defined(CONFIG_MPC831X)
/* SPCR bits - MPC831x specific */
#define SPCR_TSECDP			0x00003000	/* TSEC data priority */
#define SPCR_TSECDP_SHIFT		(31-19)
#define SPCR_TSECEP			0x00000C00	/* TSEC emergency priority */
#define SPCR_TSECEP_SHIFT		(31-21)
#define SPCR_TSECBDP			0x00000300	/* TSEC buffer descriptor priority */
#define SPCR_TSECBDP_SHIFT		(31-23)
#endif

/* SICRL/H - System I/O Configuration Register Low/High
 */
#if defined(CONFIG_MPC834X)
/* SICRL bits - MPC8349 specific */
#define SICRL_LDP_A			0x80000000
#define SICRL_USB1			0x40000000
#define SICRL_USB0			0x20000000
#define SICRL_UART			0x0C000000
#define SICRL_GPIO1_A			0x02000000
#define SICRL_GPIO1_B			0x01000000
#define SICRL_GPIO1_C			0x00800000
#define SICRL_GPIO1_D			0x00400000
#define SICRL_GPIO1_E			0x00200000
#define SICRL_GPIO1_F			0x00180000
#define SICRL_GPIO1_G			0x00040000
#define SICRL_GPIO1_H			0x00020000
#define SICRL_GPIO1_I			0x00010000
#define SICRL_GPIO1_J			0x00008000
#define SICRL_GPIO1_K			0x00004000
#define SICRL_GPIO1_L			0x00003000

/* SICRH bits - MPC8349 specific */
#define SICRH_DDR			0x80000000
#define SICRH_TSEC1_A			0x10000000
#define SICRH_TSEC1_B			0x08000000
#define SICRH_TSEC1_C			0x04000000
#define SICRH_TSEC1_D			0x02000000
#define SICRH_TSEC1_E			0x01000000
#define SICRH_TSEC1_F			0x00800000
#define SICRH_TSEC2_A			0x00400000
#define SICRH_TSEC2_B			0x00200000
#define SICRH_TSEC2_C			0x00100000
#define SICRH_TSEC2_D			0x00080000
#define SICRH_TSEC2_E			0x00040000
#define SICRH_TSEC2_F			0x00020000
#define SICRH_TSEC2_G			0x00010000
#define SICRH_TSEC2_H			0x00008000
#define SICRH_GPIO2_A			0x00004000
#define SICRH_GPIO2_B			0x00002000
#define SICRH_GPIO2_C			0x00001000
#define SICRH_GPIO2_D			0x00000800
#define SICRH_GPIO2_E			0x00000400
#define SICRH_GPIO2_F			0x00000200
#define SICRH_GPIO2_G			0x00000180
#define SICRH_GPIO2_H			0x00000060
#define SICRH_TSOBI1			0x00000002
#define SICRH_TSOBI2			0x00000001

#elif defined(CONFIG_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A			0xC0000000
#define SICRL_LCLK_1			0x10000000
#define SICRL_LCLK_2			0x08000000
#define SICRL_SRCID_A			0x03000000
#define SICRL_IRQ_CKSTP_A		0x00C00000

/* SICRH bits - MPC8360 specific */
#define SICRH_DDR			0x80000000
#define SICRH_SECONDARY_DDR		0x40000000
#define SICRH_SDDROE			0x20000000
#define SICRH_IRQ3			0x10000000
#define SICRH_UC1EOBI			0x00000004
#define SICRH_UC2E1OBI			0x00000002
#define SICRH_UC2E2OBI			0x00000001

#elif defined(CONFIG_MPC832X)
/* SICRL bits - MPC832X specific */
#define SICRL_LDP_LCS_A			0x80000000
#define SICRL_IRQ_CKS			0x20000000
#define SICRL_PCI_MSRC			0x10000000
#define SICRL_URT_CTPR			0x06000000
#define SICRL_IRQ_CTPR			0x00C00000

#elif defined(CONFIG_MPC831X)
/* SICRL bits - MPC831x specific */
#define SICRL_LBC			0x30000000
#define SICRL_UART			0x0C000000
#define SICRL_SPI_A			0x03000000
#define SICRL_SPI_B			0x00C00000
#define SICRL_SPI_C			0x00300000
#define SICRL_SPI_D			0x000C0000
#define SICRL_USBDR			0x00000C00
#define SICRL_ETSEC1_A			0x0000000C
#define SICRL_ETSEC2_A			0x00000003

/* SICRH bits - MPC831x specific */
#define SICRH_INTR_A			0x02000000
#define SICRH_INTR_B			0x00C00000
#define SICRH_IIC			0x00300000
#define SICRH_ETSEC2_B			0x000C0000
#define SICRH_ETSEC2_C			0x00030000
#define SICRH_ETSEC2_D			0x0000C000
#define SICRH_ETSEC2_E			0x00003000
#define SICRH_ETSEC2_F			0x00000C00
#define SICRH_ETSEC2_G			0x00000300
#define SICRH_ETSEC1_B			0x00000080
#define SICRH_ETSEC1_C			0x00000060
#define SICRH_GTX1_DLY			0x00000008
#define SICRH_GTX2_DLY			0x00000004
#define SICRH_TSOBI1			0x00000002
#define SICRH_TSOBI2			0x00000001

#endif

/* SWCRR - System Watchdog Control Register
 */
#define SWCRR				0x0204		/* Register offset to immr */
#define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
#define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
#define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
#define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
#define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)

/* SWCNR - System Watchdog Counter Register
 */
#define SWCNR				0x0208		/* Register offset to immr */
#define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
#define SWCNR_RES			~(SWCNR_SWCN)

/* SWSRR - System Watchdog Service Register
 */
#define SWSRR				0x020E		/* Register offset to immr */

/* ACR - Arbiter Configuration Register
 */
#define ACR_COREDIS			0x10000000	/* Core disable */
#define ACR_COREDIS_SHIFT		(31-7)
#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
#define ACR_PIPE_DEP_SHIFT		(31-15)
#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
#define ACR_PCI_RPTCNT_SHIFT		(31-19)
#define ACR_RPTCNT			0x00000700	/* Repeat count */
#define ACR_RPTCNT_SHIFT		(31-23)
#define ACR_APARK			0x00000030	/* Address parking */
#define ACR_APARK_SHIFT			(31-27)
#define ACR_PARKM			0x0000000F	/* Parking master */
#define ACR_PARKM_SHIFT			(31-31)

/* ATR - Arbiter Timers Register
 */
#define ATR_DTO				0x00FF0000	/* Data time out */
#define ATR_ATO				0x000000FF	/* Address time out */

/* AER - Arbiter Event Register
 */
#define AER_ETEA			0x00000020	/* Transfer error */
#define AER_RES				0x00000010	/* Reserved transfer type */
#define AER_ECW				0x00000008	/* External control word transfer type */
#define AER_AO				0x00000004	/* Address Only transfer type */
#define AER_DTO				0x00000002	/* Data time out */
#define AER_ATO				0x00000001	/* Address time out */

/* AEATR - Arbiter Event Address Register
 */
#define AEATR_EVENT			0x07000000	/* Event type */
#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
#define AEATR_TBST			0x00000800	/* Transfer burst */
#define AEATR_TSIZE			0x00000700	/* Transfer Size */
#define AEATR_TTYPE			0x0000001F	/* Transfer Type */

/* HRCWL - Hard Reset Configuration Word Low
 */
#define HRCWL_LBIUCM			0x80000000
#define HRCWL_LBIUCM_SHIFT		31
#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000

#define HRCWL_DDRCM			0x40000000
#define HRCWL_DDRCM_SHIFT		30
#define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
#define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000

#define HRCWL_SPMF			0x0f000000
#define HRCWL_SPMF_SHIFT		24
#define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
#define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
#define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
#define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
#define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
#define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
#define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
#define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
#define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
#define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
#define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
#define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
#define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
#define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
#define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
#define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000

#define HRCWL_VCO_BYPASS		0x00000000
#define HRCWL_VCO_1X2			0x00000000
#define HRCWL_VCO_1X4			0x00200000
#define HRCWL_VCO_1X8			0x00400000

#define HRCWL_COREPLL			0x007F0000
#define HRCWL_COREPLL_SHIFT		16
#define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
#define HRCWL_CORE_TO_CSB_1X1		0x00020000
#define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
#define HRCWL_CORE_TO_CSB_2X1		0x00040000
#define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
#define HRCWL_CORE_TO_CSB_3X1		0x00060000

#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
#define HRCWL_CEVCOD			0x000000C0
#define HRCWL_CEVCOD_SHIFT		6
#define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
#define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
#define HRCWL_CE_PLL_VCO_DIV_2		0x00000080

#define HRCWL_CEPDF			0x00000020
#define HRCWL_CEPDF_SHIFT		5
#define HRCWL_CE_PLL_DIV_1X1		0x00000000
#define HRCWL_CE_PLL_DIV_2X1		0x00000020

#define HRCWL_CEPMF			0x0000001F
#define HRCWL_CEPMF_SHIFT		0
#define HRCWL_CE_TO_PLL_1X16_		0x00000000
#define HRCWL_CE_TO_PLL_1X2		0x00000002
#define HRCWL_CE_TO_PLL_1X3		0x00000003
#define HRCWL_CE_TO_PLL_1X4		0x00000004
#define HRCWL_CE_TO_PLL_1X5		0x00000005
#define HRCWL_CE_TO_PLL_1X6		0x00000006
#define HRCWL_CE_TO_PLL_1X7		0x00000007
#define HRCWL_CE_TO_PLL_1X8		0x00000008
#define HRCWL_CE_TO_PLL_1X9		0x00000009
#define HRCWL_CE_TO_PLL_1X10		0x0000000A
#define HRCWL_CE_TO_PLL_1X11		0x0000000B
#define HRCWL_CE_TO_PLL_1X12		0x0000000C
#define HRCWL_CE_TO_PLL_1X13		0x0000000D
#define HRCWL_CE_TO_PLL_1X14		0x0000000E
#define HRCWL_CE_TO_PLL_1X15		0x0000000F
#define HRCWL_CE_TO_PLL_1X16		0x00000010
#define HRCWL_CE_TO_PLL_1X17		0x00000011
#define HRCWL_CE_TO_PLL_1X18		0x00000012
#define HRCWL_CE_TO_PLL_1X19		0x00000013
#define HRCWL_CE_TO_PLL_1X20		0x00000014
#define HRCWL_CE_TO_PLL_1X21		0x00000015
#define HRCWL_CE_TO_PLL_1X22		0x00000016
#define HRCWL_CE_TO_PLL_1X23		0x00000017
#define HRCWL_CE_TO_PLL_1X24		0x00000018
#define HRCWL_CE_TO_PLL_1X25		0x00000019
#define HRCWL_CE_TO_PLL_1X26		0x0000001A
#define HRCWL_CE_TO_PLL_1X27		0x0000001B
#define HRCWL_CE_TO_PLL_1X28		0x0000001C
#define HRCWL_CE_TO_PLL_1X29		0x0000001D
#define HRCWL_CE_TO_PLL_1X30		0x0000001E
#define HRCWL_CE_TO_PLL_1X31		0x0000001F
#endif

/* HRCWH - Hardware Reset Configuration Word High
 */
#define HRCWH_PCI_HOST			0x80000000
#define HRCWH_PCI_HOST_SHIFT		31
#define HRCWH_PCI_AGENT			0x00000000

#if defined(CONFIG_MPC834X)
#define HRCWH_32_BIT_PCI		0x00000000
#define HRCWH_64_BIT_PCI		0x40000000
#endif

#define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
#define HRCWH_PCI1_ARBITER_ENABLE	0x20000000

#define HRCWH_PCI_ARBITER_DISABLE	0x00000000
#define HRCWH_PCI_ARBITER_ENABLE	0x20000000

#if defined(CONFIG_MPC834X)
#define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE	0x10000000

#elif defined(CONFIG_MPC8360)
#define HRCWH_PCICKDRV_DISABLE		0x00000000
#define HRCWH_PCICKDRV_ENABLE		0x10000000
#endif

#define HRCWH_CORE_DISABLE		0x08000000
#define HRCWH_CORE_ENABLE		0x00000000

#define HRCWH_FROM_0X00000100		0x00000000
#define HRCWH_FROM_0XFFF00100		0x04000000

#define HRCWH_BOOTSEQ_DISABLE		0x00000000
#define HRCWH_BOOTSEQ_NORMAL		0x01000000