📄 ppc4xx_enet.h

📁 U-boot源码 ARM7启动代码
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/* TAH Mode Register */#define TAH_MR_CVR		(0x80000000)	    /* Checksum verification on RX */#define TAH_MR_SR		(0x40000000)	    /* Software reset */#define TAH_MR_ST		(0x3F000000)	    /* Send Threshold */#define TAH_MR_TFS		(0x00E00000)	    /* Transmit FIFO size */#define TAH_MR_DTFP		(0x00100000)	    /* Disable TX FIFO parity */#define TAH_MR_DIG		(0x00080000)	    /* Disable interrupt generation */#define TAH_MR_RSVD		(0x0007FFFF)	    /* Reserved */#define TAH_MR_ST_V		(20)#define TAH_MR_TFS_V		(17)#define TAH_MR_TFS_2K		(0x1)		    /* Transmit FIFO size 2Kbyte */#define TAH_MR_TFS_4K		(0x2)		    /* Transmit FIFO size 4Kbyte */#define TAH_MR_TFS_6K		(0x3)		    /* Transmit FIFO size 6Kbyte */#define TAH_MR_TFS_8K		(0x4)		    /* Transmit FIFO size 8Kbyte */#define TAH_MR_TFS_10K		(0x5)		    /* Transmit FIFO size 10Kbyte (max)*//* TAH Segment Size Registers 0:5 */#define TAH_SSR_RSVD0		(0xC0000000)	    /* Reserved */#define TAH_SSR_SS		(0x3FFE0000)	    /* Segment size in multiples of 2 */#define TAH_SSR_RSVD1		(0x0001FFFF)	    /* Reserved *//* TAH Transmit Status Register */#define TAH_TSR_TFTS		(0x80000000)	    /* Transmit FIFO too small */#define TAH_TSR_UH		(0x40000000)	    /* Unrecognized header */#define TAH_TSR_NIPF		(0x20000000)	    /* Not IPv4 */#define TAH_TSR_IPOP		(0x10000000)	    /* IP option present */#define TAH_TSR_NISF		(0x08000000)	    /* No IEEE SNAP format */#define TAH_TSR_ILTS		(0x04000000)	    /* IP length too short */#define TAH_TSR_IPFP		(0x02000000)	    /* IP fragment present */#define TAH_TSR_UP		(0x01000000)	    /* Unsupported protocol */#define TAH_TSR_TFP		(0x00800000)	    /* TCP flags present */#define TAH_TSR_SUDP		(0x00400000)	    /* Segmentation for UDP */#define TAH_TSR_DLM		(0x00200000)	    /* Data length mismatch */#define TAH_TSR_SIEEE		(0x00100000)	    /* Segmentation for IEEE */#define TAH_TSR_TFPE		(0x00080000)	    /* Transmit FIFO parity error */#define TAH_TSR_SSTS		(0x00040000)	    /* Segment size too small */#define TAH_TSR_RSVD		(0x0003FFFF)	    /* Reserved */#endif /* CONFIG_440GX *//* Ethernet MAC Regsiter Addresses */#if defined(CONFIG_440)#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0E00)#else#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0800)#endif#else#if defined(CONFIG_405EZ)#define EMAC_BASE 		0xEF600900#else#define EMAC_BASE 		0xEF600800#endif#endif#define EMAC_M0			(EMAC_BASE)#define EMAC_M1			(EMAC_BASE + 4)#define EMAC_TXM0		(EMAC_BASE + 8)#define EMAC_TXM1		(EMAC_BASE + 12)#define EMAC_RXM		(EMAC_BASE + 16)#define EMAC_ISR		(EMAC_BASE + 20)#define EMAC_IER		(EMAC_BASE + 24)#define EMAC_IAH		(EMAC_BASE + 28)#define EMAC_IAL		(EMAC_BASE + 32)#define EMAC_PAUSE_TIME_REG	(EMAC_BASE + 44)#define EMAC_I_FRAME_GAP_REG	(EMAC_BASE + 88)#define EMAC_STACR		(EMAC_BASE + 92)#define EMAC_TRTR		(EMAC_BASE + 96)#define EMAC_RX_HI_LO_WMARK	(EMAC_BASE + 100)/* bit definitions *//* MODE REG 0 */#define EMAC_M0_RXI		(0x80000000)#define EMAC_M0_TXI		(0x40000000)#define EMAC_M0_SRST		(0x20000000)#define EMAC_M0_TXE		(0x10000000)#define EMAC_M0_RXE		(0x08000000)#define EMAC_M0_WKE		(0x04000000)/* on 440GX EMAC_MR1 has a different layout! */#if defined(CONFIG_440GX) || \    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \    defined(CONFIG_440SP) || defined(CONFIG_440SPE)/* MODE Reg 1 */#define EMAC_M1_FDE		(0x80000000)#define EMAC_M1_ILE		(0x40000000)#define EMAC_M1_VLE		(0x20000000)#define EMAC_M1_EIFC		(0x10000000)#define EMAC_M1_APP		(0x08000000)#define EMAC_M1_RSVD		(0x06000000)#define EMAC_M1_IST		(0x01000000)#define EMAC_M1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */#define EMAC_M1_MF_100MBPS	(0x00400000)#define EMAC_M1_RFS_16K		(0x00280000)	/* ~4k for 512 byte */#define EMAC_M1_RFS_8K		(0x00200000)	/* ~4k for 512 byte */#define EMAC_M1_RFS_4K		(0x00180000)	/* ~4k for 512 byte */#define EMAC_M1_RFS_2K		(0x00100000)#define EMAC_M1_RFS_1K		(0x00080000)#define EMAC_M1_TX_FIFO_16K	(0x00050000)	/* 0's for 512 byte */#define EMAC_M1_TX_FIFO_8K	(0x00040000)#define EMAC_M1_TX_FIFO_4K	(0x00030000)#define EMAC_M1_TX_FIFO_2K	(0x00020000)#define EMAC_M1_TX_FIFO_1K	(0x00010000)#define EMAC_M1_TR_MULTI	(0x00008000)	/* 0'x for single packet */#define EMAC_M1_MWSW		(0x00007000)#define EMAC_M1_JUMBO_ENABLE	(0x00000800)#define EMAC_M1_IPPA		(0x000007c0)#define EMAC_M1_OBCI_GT100	(0x00000020)#define EMAC_M1_OBCI_100	(0x00000018)#define EMAC_M1_OBCI_83		(0x00000010)#define EMAC_M1_OBCI_66		(0x00000008)#define EMAC_M1_RSVD1		(0x00000007)#else /* defined(CONFIG_440GX) *//* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */#define EMAC_M1_FDE		0x80000000#define EMAC_M1_ILE		0x40000000#define EMAC_M1_VLE		0x20000000#define EMAC_M1_EIFC		0x10000000#define EMAC_M1_APP		0x08000000#define EMAC_M1_AEMI		0x02000000#define EMAC_M1_IST		0x01000000#define EMAC_M1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */#define EMAC_M1_MF_100MBPS	0x00400000#define EMAC_M1_RFS_4K		0x00300000	/* ~4k for 512 byte */#define EMAC_M1_RFS_2K		0x00200000#define EMAC_M1_RFS_1K		0x00100000#define EMAC_M1_TX_FIFO_2K	0x00080000	/* 0's for 512 byte */#define EMAC_M1_TX_FIFO_1K	0x00040000#define EMAC_M1_TR0_DEPEND	0x00010000	/* 0'x for single packet */#define EMAC_M1_TR0_MULTI	0x00008000#define EMAC_M1_TR1_DEPEND	0x00004000#define EMAC_M1_TR1_MULTI	0x00002000#if defined(CONFIG_440EP) || defined(CONFIG_440GR)#define EMAC_M1_JUMBO_ENABLE	0x00001000#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */#endif /* defined(CONFIG_440GX) *//* Transmit Mode Register 0 */#define EMAC_TXM0_GNP0		(0x80000000)#define EMAC_TXM0_GNP1		(0x40000000)#define EMAC_TXM0_GNPD		(0x20000000)#define EMAC_TXM0_FC		(0x10000000)/* Receive Mode Register */#define EMAC_RMR_SP		(0x80000000)#define EMAC_RMR_SFCS		(0x40000000)#define EMAC_RMR_ARRP		(0x20000000)#define EMAC_RMR_ARP		(0x10000000)#define EMAC_RMR_AROP		(0x08000000)#define EMAC_RMR_ARPI		(0x04000000)#define EMAC_RMR_PPP		(0x02000000)#define EMAC_RMR_PME		(0x01000000)#define EMAC_RMR_PMME		(0x00800000)#define EMAC_RMR_IAE		(0x00400000)#define EMAC_RMR_MIAE		(0x00200000)#define EMAC_RMR_BAE		(0x00100000)#define EMAC_RMR_MAE		(0x00080000)/* Interrupt Status & enable Regs */#define EMAC_ISR_OVR		(0x02000000)#define EMAC_ISR_PP		(0x01000000)#define EMAC_ISR_BP		(0x00800000)#define EMAC_ISR_RP		(0x00400000)#define EMAC_ISR_SE		(0x00200000)#define EMAC_ISR_SYE		(0x00100000)#define EMAC_ISR_BFCS		(0x00080000)#define EMAC_ISR_PTLE		(0x00040000)#define EMAC_ISR_ORE		(0x00020000)#define EMAC_ISR_IRE		(0x00010000)#define EMAC_ISR_DBDM		(0x00000200)#define EMAC_ISR_DB0		(0x00000100)#define EMAC_ISR_SE0		(0x00000080)#define EMAC_ISR_TE0		(0x00000040)#define EMAC_ISR_DB1		(0x00000020)#define EMAC_ISR_SE1		(0x00000010)#define EMAC_ISR_TE1		(0x00000008)#define EMAC_ISR_MOS		(0x00000002)#define EMAC_ISR_MOF		(0x00000001)/* STA CONTROL REG */#define EMAC_STACR_OC		(0x00008000)#define EMAC_STACR_PHYE		(0x00004000)#ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */#define EMAC_STACR_INDIRECT_MODE (0x00002000)#define EMAC_STACR_WRITE	(0x00000800) /* $BUC */#define EMAC_STACR_READ		(0x00001000) /* $BUC */#define EMAC_STACR_OP_MASK	(0x00001800)#define EMAC_STACR_MDIO_ADDR	(0x00000000)#define EMAC_STACR_MDIO_WRITE	(0x00000800)#define EMAC_STACR_MDIO_READ	(0x00001800)#define EMAC_STACR_MDIO_READ_INC (0x00001000)#else#define EMAC_STACR_WRITE	(0x00002000)#define EMAC_STACR_READ		(0x00001000)#endif#define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */#define EMAC_STACR_CLK_66MHZ	(0x00000400)#define EMAC_STACR_CLK_100MHZ	(0x00000C00)/* Transmit Request Threshold Register */#define EMAC_TRTR_256		(0x18000000)   /* 0's for 64 Bytes */#define EMAC_TRTR_192		(0x10000000)#define EMAC_TRTR_128		(0x01000000)/* the follwing defines are for the MadMAL status and control registers. *//* For bits 0..5 look at the mal.h file					 */#define EMAC_TX_CTRL_GFCS	(0x0200)#define EMAC_TX_CTRL_GP		(0x0100)#define EMAC_TX_CTRL_ISA	(0x0080)#define EMAC_TX_CTRL_RSA	(0x0040)#define EMAC_TX_CTRL_IVT	(0x0020)#define EMAC_TX_CTRL_RVT	(0x0010)#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)#define EMAC_TX_ST_BFCS		(0x0200)#define EMAC_TX_ST_BPP		(0x0100)#define EMAC_TX_ST_LCS		(0x0080)#define EMAC_TX_ST_ED		(0x0040)#define EMAC_TX_ST_EC		(0x0020)#define EMAC_TX_ST_LC		(0x0010)#define EMAC_TX_ST_MC		(0x0008)#define EMAC_TX_ST_SC		(0x0004)#define EMAC_TX_ST_UR		(0x0002)#define EMAC_TX_ST_SQE		(0x0001)#define EMAC_TX_ST_DEFAULT	(0x03F3)/* madmal receive status / Control bits */#define EMAC_RX_ST_OE		(0x0200)#define EMAC_RX_ST_PP		(0x0100)#define EMAC_RX_ST_BP		(0x0080)#define EMAC_RX_ST_RP		(0x0040)#define EMAC_RX_ST_SE		(0x0020)#define EMAC_RX_ST_AE		(0x0010)#define EMAC_RX_ST_BFCS		(0x0008)#define EMAC_RX_ST_PTL		(0x0004)#define EMAC_RX_ST_ORE		(0x0002)#define EMAC_RX_ST_IRE		(0x0001)/* all the errors we care about */#define EMAC_RX_ERRORS		(0x03FF)#endif /* _PPC4XX_ENET_H_ */
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