immap_5329.h

U-boot源码 ARM7启动代码

	u8 sr;			/* 0x0C status register */
	u8 res4[3];		/* 0x0D - 0x0F */
	u8 dr;			/* 0x10 data register */
	u8 res5[3];		/* 0x11 - 0x13 */
} i2c_t;

/* QSPI module registers */
typedef struct qspi_ctrl {
	u16 qmr;		/* Mode register */
	u16 res1;
	u16 qdlyr;		/* Delay register */
	u16 res2;
	u16 qwr;		/* Wrap register */
	u16 res3;
	u16 qir;		/* Interrupt register */
	u16 res4;
	u16 qar;		/* Address register */
	u16 res5;
	u16 qdr;		/* Data register */
	u16 res6;
} qspi_t;

/* PWM module registers */
typedef struct pwm_ctrl {
	u8 en;			/* 0x00 PWM Enable Register */
	u8 pol;			/* 0x01 Polarity Register */
	u8 clk;			/* 0x02 Clock Select Register */
	u8 prclk;		/* 0x03 Prescale Clock Select Register */
	u8 cae;			/* 0x04 Center Align Enable Register */
	u8 ctl;			/* 0x05 Control Register */
	u8 res1[2];		/* 0x06 - 0x07 */
	u8 scla;		/* 0x08 Scale A register */
	u8 sclb;		/* 0x09 Scale B register */
	u8 res2[2];		/* 0x0A - 0x0B */
	u8 cnt0;		/* 0x0C Channel 0 Counter register */
	u8 cnt1;		/* 0x0D Channel 1 Counter register */
	u8 cnt2;		/* 0x0E Channel 2 Counter register */
	u8 cnt3;		/* 0x0F Channel 3 Counter register */
	u8 cnt4;		/* 0x10 Channel 4 Counter register */
	u8 cnt5;		/* 0x11 Channel 5 Counter register */
	u8 cnt6;		/* 0x12 Channel 6 Counter register */
	u8 cnt7;		/* 0x13 Channel 7 Counter register */
	u8 per0;		/* 0x14 Channel 0 Period register */
	u8 per1;		/* 0x15 Channel 1 Period register */
	u8 per2;		/* 0x16 Channel 2 Period register */
	u8 per3;		/* 0x17 Channel 3 Period register */
	u8 per4;		/* 0x18 Channel 4 Period register */
	u8 per5;		/* 0x19 Channel 5 Period register */
	u8 per6;		/* 0x1A Channel 6 Period register */
	u8 per7;		/* 0x1B Channel 7 Period register */
	u8 dty0;		/* 0x1C Channel 0 Duty register */
	u8 dty1;		/* 0x1D Channel 1 Duty register */
	u8 dty2;		/* 0x1E Channel 2 Duty register */
	u8 dty3;		/* 0x1F Channel 3 Duty register */
	u8 dty4;		/* 0x20 Channel 4 Duty register */
	u8 dty5;		/* 0x21 Channel 5 Duty register */
	u8 dty6;		/* 0x22 Channel 6 Duty register */
	u8 dty7;		/* 0x23 Channel 7 Duty register */
	u8 sdn;			/* 0x24 Shutdown register */
	u8 res3[3];		/* 0x25 - 0x27 */
} pwm_t;

/* Edge Port module registers */
typedef struct eport_ctrl {
	u16 par;		/* 0x00 Pin Assignment Register */
	u8 ddar;		/* 0x02 Data Direction Register */
	u8 ier;			/* 0x03 Interrupt Enable Register */
	u8 dr;			/* 0x04 Data Register */
	u8 pdr;			/* 0x05 Pin Data  Register */
	u8 fr;			/* 0x06 Flag_Register */
	u8 res1;
} eport_t;

/* Watchdog registers */
typedef struct wdog_ctrl {
	u16 cr;			/* 0x00 Control register */
	u16 mr;			/* 0x02 Modulus register */
	u16 cntr;		/* 0x04 Count register */
	u16 sr;			/* 0x06 Service register */
} wdog_t;

/*Chip configuration module registers */
typedef struct ccm_ctrl {
	u16 ccr;		/* 0x00 Chip configuration register */
	u16 res2;		/* 0x02 */
	u16 rcon;		/* 0x04 Rreset configuration register */
	u16 cir;		/* 0x06 Chip identification register */
	u32 res3;		/* 0x08 */
	u16 misccr;		/* 0x0A Miscellaneous control register */
	u16 cdr;		/* 0x0C Clock divider register */
	u16 uhcsr;		/* 0x10 USB Host controller status register */
	u16 uocsr;		/* 0x12 USB On-the-Go Controller Status Reg */
} ccm_t;

typedef struct rcm {
	u8 rcr;
	u8 rsr;
} rcm_t;

/* GPIO port registers */
typedef struct gpio_ctrl {
	/* Port Output Data Registers */
	u8 podr_fech;		/* 0x00 */
	u8 podr_fecl;		/* 0x01 */
	u8 podr_ssi;		/* 0x02 */
	u8 podr_busctl;		/* 0x03 */
	u8 podr_be;		/* 0x04 */
	u8 podr_cs;		/* 0x05 */
	u8 podr_pwm;		/* 0x06 */
	u8 podr_feci2c;		/* 0x07 */
	u8 res1;		/* 0x08 */
	u8 podr_uart;		/* 0x09 */
	u8 podr_qspi;		/* 0x0A */
	u8 podr_timer;		/* 0x0B */
	u8 res2;		/* 0x0C */
	u8 podr_lcddatah;	/* 0x0D */
	u8 podr_lcddatam;	/* 0x0E */
	u8 podr_lcddatal;	/* 0x0F */
	u8 podr_lcdctlh;	/* 0x10 */
	u8 podr_lcdctll;	/* 0x11 */

	/* Port Data Direction Registers */
	u16 res3;		/* 0x12 - 0x13 */
	u8 pddr_fech;		/* 0x14 */
	u8 pddr_fecl;		/* 0x15 */
	u8 pddr_ssi;		/* 0x16 */
	u8 pddr_busctl;		/* 0x17 */
	u8 pddr_be;		/* 0x18 */
	u8 pddr_cs;		/* 0x19 */
	u8 pddr_pwm;		/* 0x1A */
	u8 pddr_feci2c;		/* 0x1B */
	u8 res4;		/* 0x1C */
	u8 pddr_uart;		/* 0x1D */
	u8 pddr_qspi;		/* 0x1E */
	u8 pddr_timer;		/* 0x1F */
	u8 res5;		/* 0x20 */
	u8 pddr_lcddatah;	/* 0x21 */
	u8 pddr_lcddatam;	/* 0x22 */
	u8 pddr_lcddatal;	/* 0x23 */
	u8 pddr_lcdctlh;	/* 0x24 */
	u8 pddr_lcdctll;	/* 0x25 */
	u16 res6;		/* 0x26 - 0x27 */

	/* Port Data Direction Registers */
	u8 ppd_fech;		/* 0x28 */
	u8 ppd_fecl;		/* 0x29 */
	u8 ppd_ssi;		/* 0x2A */
	u8 ppd_busctl;		/* 0x2B */
	u8 ppd_be;		/* 0x2C */
	u8 ppd_cs;		/* 0x2D */
	u8 ppd_pwm;		/* 0x2E */
	u8 ppd_feci2c;		/* 0x2F */
	u8 res7;		/* 0x30 */
	u8 ppd_uart;		/* 0x31 */
	u8 ppd_qspi;		/* 0x32 */
	u8 ppd_timer;		/* 0x33 */
	u8 res8;		/* 0x34 */
	u8 ppd_lcddatah;	/* 0x35 */
	u8 ppd_lcddatam;	/* 0x36 */
	u8 ppd_lcddatal;	/* 0x37 */
	u8 ppd_lcdctlh;		/* 0x38 */
	u8 ppd_lcdctll;		/* 0x39 */
	u16 res9;		/* 0x3A - 0x3B */

	/* Port Clear Output Data Registers */
	u8 pclrr_fech;		/* 0x3C */
	u8 pclrr_fecl;		/* 0x3D */
	u8 pclrr_ssi;		/* 0x3E */
	u8 pclrr_busctl;	/* 0x3F */
	u8 pclrr_be;		/* 0x40 */
	u8 pclrr_cs;		/* 0x41 */
	u8 pclrr_pwm;		/* 0x42 */
	u8 pclrr_feci2c;	/* 0x43 */
	u8 res10;		/* 0x44 */
	u8 pclrr_uart;		/* 0x45 */
	u8 pclrr_qspi;		/* 0x46 */
	u8 pclrr_timer;		/* 0x47 */
	u8 res11;		/* 0x48 */
	u8 pclrr_lcddatah;	/* 0x49 */
	u8 pclrr_lcddatam;	/* 0x4A */
	u8 pclrr_lcddatal;	/* 0x4B */
	u8 pclrr_lcdctlh;	/* 0x4C */
	u8 pclrr_lcdctll;	/* 0x4D */
	u16 res12;		/* 0x4E - 0x4F */

	/* Pin Assignment Registers */
	u8 par_fec;		/* 0x50 */
	u8 par_pwm;		/* 0x51 */
	u8 par_busctl;		/* 0x52 */
	u8 par_feci2c;		/* 0x53 */
	u8 par_be;		/* 0x54 */
	u8 par_cs;		/* 0x55 */
	u16 par_ssi;		/* 0x56 */
	u16 par_uart;		/* 0x58 */
	u16 par_qspi;		/* 0x5A */
	u8 par_timer;		/* 0x5C */
	u8 par_lcddata;		/* 0x5D */
	u16 par_lcdctl;		/* 0x5E */
	u16 par_irq;		/* 0x60 */
	u16 res16;		/* 0x62 - 0x63 */

	/* Mode Select Control Registers */
	u8 mscr_flexbus;	/* 0x64 */
	u8 mscr_sdram;		/* 0x65 */
	u16 res17;		/* 0x66 - 0x67 */

	/* Drive Strength Control Registers */
	u8 dscr_i2c;		/* 0x68 */
	u8 dscr_pwm;		/* 0x69 */
	u8 dscr_fec;		/* 0x6A */
	u8 dscr_uart;		/* 0x6B */
	u8 dscr_qspi;		/* 0x6C */
	u8 dscr_timer;		/* 0x6D */
	u8 dscr_ssi;		/* 0x6E */
	u8 dscr_lcd;		/* 0x6F */
	u8 dscr_debug;		/* 0x70 */
	u8 dscr_clkrst;		/* 0x71 */
	u8 dscr_irq;		/* 0x72 */
} gpio_t;

/* LCD module registers */
typedef struct lcd_ctrl {
	u32 ssar;		/* 0x00 Screen Start Address Register */
	u32 sr;			/* 0x04 LCD Size Register */
	u32 vpw;		/* 0x08 Virtual Page Width Register */
	u32 cpr;		/* 0x0C Cursor Position Register */
	u32 cwhb;		/* 0x10 Cursor Width Height and Blink Register */
	u32 ccmr;		/* 0x14 Color Cursor Mapping Register */
	u32 pcr;		/* 0x18 Panel Configuration Register */
	u32 hcr;		/* 0x1C Horizontal Configuration Register */
	u32 vcr;		/* 0x20 Vertical Configuration Register */
	u32 por;		/* 0x24 Panning Offset Register */
	u32 scr;		/* 0x28 Sharp Configuration Register */
	u32 pccr;		/* 0x2C PWM Contrast Control Register */
	u32 dcr;		/* 0x30 DMA Control Register */
	u32 rmcr;		/* 0x34 Refresh Mode Control Register */
	u32 icr;		/* 0x38 Refresh Mode Control Register */
	u32 ier;		/* 0x3C Interrupt Enable Register */
	u32 isr;		/* 0x40 Interrupt Status Register */
	u32 res[4];
	u32 gwsar;		/* 0x50 Graphic Window Start Address Register */
	u32 gwsr;		/* 0x54 Graphic Window Size Register */
	u32 gwvpw;		/* 0x58 Graphic Window Virtual Page Width Register */
	u32 gwpor;		/* 0x5C Graphic Window Panning Offset Register */
	u32 gwpr;		/* 0x60 Graphic Window Position Register */
	u32 gwcr;		/* 0x64 Graphic Window Control Register */
	u32 gwdcr;		/* 0x68 Graphic Window DMA Control Register */
} lcd_t;

typedef struct lcdbg_ctrl {
	u32 bglut[255];
} lcdbg_t;

typedef struct lcdgw_ctrl {
	u32 gwlut[255];
} lcdgw_t;

/* USB OTG module registers */
typedef struct usb_otg {
	u32 id;			/* 0x000 Identification Register */
	u32 hwgeneral;		/* 0x004 General HW Parameters */
	u32 hwhost;		/* 0x008 Host HW Parameters */
	u32 hwdev;		/* 0x00C Device HW parameters */
	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
	u32 res1[58];		/* 0x18 - 0xFF */
	u8 caplength;		/* 0x100 Capability Register Length */
	u8 res2;		/* 0x101 */
	u16 hciver;		/* 0x102 Host Interface Version Number */
	u32 hcsparams;		/* 0x104 Host Structural Parameters */
	u32 hccparams;		/* 0x108 Host Capability Parameters */
	u32 res3[5];		/* 0x10C - 0x11F */
	u16 dciver;		/* 0x120 Device Interface Version Number */
	u16 res4;		/* 0x122 */
	u32 dccparams;		/* 0x124 Device Capability Parameters */
	u32 res5[6];		/* 0x128 - 0x13F */
	u32 cmd;		/* 0x140 USB Command */
	u32 sts;		/* 0x144 USB Status */
	u32 intr;		/* 0x148 USB Interrupt Enable */
	u32 frindex;		/* 0x14C USB Frame Index */
	u32 res6;		/* 0x150 */
	u32 prd_dev;		/* 0x154 Periodic Frame List Base or Device Address */
	u32 aync_ep;		/* 0x158 Current Asynchronous List or Address at Endpoint List Address */
	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control */
	u32 burstsize;		/* 0x160 Master Interface Data Burst Size */
	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control */
	u32 res7[6];		/* 0x168 - 0x17F */
	u32 cfgflag;		/* 0x180 Configure Flag Register */
	u32 portsc1;		/* 0x184 Port Status/Control */
	u32 res8[7];		/* 0x188 - 0x1A3 */
	u32 otgsc;		/* 0x1A4 On The Go Status and Control */
	u32 mode;		/* 0x1A8 USB mode register */
	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
	u32 eptprime;		/* 0x1B0 Endpoint initialization */
	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
	u32 eptstat;		/* 0x1B8 Endpoint status */
	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
} usbotg_t;

/* USB Host module registers */
typedef struct usb_host {
	u32 id;			/* 0x000 Identification Register */
	u32 hwgeneral;		/* 0x004 General HW Parameters */
	u32 hwhost;		/* 0x008 Host HW Parameters */
	u32 res1;		/* 0x0C */
	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
	u32 res2[58];		/* 0x18 - 0xFF */

	/* Host Controller Capability Register */
	u8 caplength;		/* 0x100 Capability Register Length */
	u8 res3;		/* 0x101 */
	u16 hciver;		/* 0x102 Host Interface Version Number */
	u32 hcsparams;		/* 0x104 Host Structural Parameters */
	u32 hccparams;		/* 0x108 Host Capability Parameters */
	u32 res4[13];		/* 0x10C - 0x13F */

	/* Host Controller Operational Register */
	u32 cmd;		/* 0x140 USB Command */
	u32 sts;		/* 0x144 USB Status */
	u32 intr;		/* 0x148 USB Interrupt Enable */
	u32 frindex;		/* 0x14C USB Frame Index */
	u32 res5;		/* 0x150 (ctrl segment register in EHCI spec) */
	u32 prdlst;		/* 0x154 Periodic Frame List Base Address */
	u32 aynclst;		/* 0x158 Current Asynchronous List Address */
	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
	u32 burstsize;		/* 0x160 Master Interface Data Burst Size (non-ehci) */
	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control  (non-ehci) */
	u32 res6[6];		/* 0x168 - 0x17F */
	u32 cfgflag;		/* 0x180 Configure Flag Register */
	u32 portsc1;		/* 0x184 Port Status/Control */
	u32 res7[8];		/* 0x188 - 0x1A7 */

	/* non-ehci registers */
	u32 mode;		/* 0x1A8 USB mode register */
	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
	u32 eptprime;		/* 0x1B0 Endpoint initialization */
	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
	u32 eptstat;		/* 0x1B8 Endpoint status */
	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
} usbhost_t;

/* SDRAM controller registers */
typedef struct sdram_ctrl {
	u32 mode;		/* 0x00 Mode/Extended Mode register */
	u32 ctrl;		/* 0x04 Control register */
	u32 cfg1;		/* 0x08 Configuration register 1 */
	u32 cfg2;		/* 0x0C Configuration register 2 */
	u32 res1[64];		/* 0x10 - 0x10F */
	u32 cs0;		/* 0x110 Chip Select 0 Configuration */
	u32 cs1;		/* 0x114 Chip Select 1 Configuration */
} sdram_t;

/* Synchronous serial interface */
typedef struct ssi_ctrl {
	u32 tx0;		/* 0x00 Transmit Data Register 0 */
	u32 tx1;		/* 0x04 Transmit Data Register 1 */
	u32 rx0;		/* 0x08 Receive Data Register 0 */
	u32 rx1;		/* 0x0C Receive Data Register 1 */
	u32 cr;			/* 0x10 Control Register */
	u32 isr;		/* 0x14 Interrupt Status Register */
	u32 ier;		/* 0x18 Interrupt Enable Register */
	u32 tcr;		/* 0x1C Transmit Configuration Register */
	u32 rcr;		/* 0x20 Receive Configuration Register */
	u32 ccr;		/* 0x24 Clock Control Register */
	u32 res1;		/* 0x28 */
	u32 fcsr;		/* 0x2C FIFO Control/Status Register */
	u32 res2[2];		/* 0x30 - 0x37 */
	u32 acr;		/* 0x38 AC97 Control Register */
	u32 acadd;		/* 0x3C AC97 Command Address Register */
	u32 acdat;		/* 0x40 AC97 Command Data Register */
	u32 atag;		/* 0x44 AC97 Tag Register */
	u32 tmask;		/* 0x48 Transmit Time Slot Mask Register */
	u32 rmask;		/* 0x4C Receive Time Slot Mask Register */
} ssi_t;

/* Clock Module registers */
typedef struct pll_ctrl {
	u8 podr;		/* 0x00 Output Divider Register */
	u8 res1[3];
	u8 pcr;			/* 0x04 Control Register */
	u8 res2[3];
	u8 pmdr;		/* 0x08 Modulation Divider Register */
	u8 res3[3];
	u8 pfdr;		/* 0x0C Feedback Divider Register */
	u8 res4[3];
} pll_t;

#endif				/* __IMMAP_5329__ */