immap_5329.h

U-boot源码 ARM7启动代码

/*
 * MCF5329 Internal Memory Map
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([e-mail])
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __IMMAP_5329__
#define __IMMAP_5329__

#define MMAP_SCM1	0xEC000000
#define MMAP_MDHA	0xEC080000
#define MMAP_SKHA	0xEC084000
#define MMAP_RNG	0xEC088000
#define MMAP_SCM2	0xFC000000
#define MMAP_XBS	0xFC004000
#define MMAP_FBCS	0xFC008000
#define MMAP_CAN	0xFC020000
#define MMAP_FEC	0xFC030000
#define MMAP_SCM3	0xFC040000
#define MMAP_EDMA	0xFC044000
#define MMAP_TCD	0xFC045000
#define MMAP_INTC0	0xFC048000
#define MMAP_INTC1	0xFC04C000
#define MMAP_INTCACK	0xFC054000
#define MMAP_I2C	0xFC058000
#define MMAP_QSPI	0xFC05C000
#define MMAP_UART0	0xFC060000
#define MMAP_UART1	0xFC064000
#define MMAP_UART2	0xFC068000
#define MMAP_DTMR0	0xFC070000
#define MMAP_DTMR1	0xFC074000
#define MMAP_DTMR2	0xFC078000
#define MMAP_DTMR3	0xFC07C000
#define MMAP_PIT0	0xFC080000
#define MMAP_PIT1	0xFC084000
#define MMAP_PIT2	0xFC088000
#define MMAP_PIT3	0xFC08C000
#define MMAP_PWM	0xFC090000
#define MMAP_EPORT	0xFC094000
#define MMAP_WDOG	0xFC098000
#define MMAP_RCM	0xFC0A0000
#define MMAP_CCM	0xFC0A0004
#define MMAP_GPIO	0xFC0A4000
#define MMAP_RTC	0xFC0A8000
#define MMAP_LCDC	0xFC0AC000
#define MMAP_USBOTG	0xFC0B0000
#define MMAP_USBH	0xFC0B4000
#define MMAP_SDRAM	0xFC0B8000
#define MMAP_SSI	0xFC0BC000
#define MMAP_PLL	0xFC0C0000

/* System control module registers */
typedef struct scm1_ctrl {
	u32 mpr0;		/* 0x00 Master Privilege Register 0 */
	u32 res1[15];		/* 0x04 - 0x3F */
	u32 pacrh;		/* 0x40 Peripheral Access Control Register H */
	u32 res2[3];		/* 0x44 - 0x53 */
	u32 bmt0;		/*0x54 Bus Monitor Timeout 0 */
} scm1_t;

/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
	u32 mdmr;		/* 0x00 MDHA Mode Register */
	u32 mdcr;		/* 0x04 Control register */
	u32 mdcmr;		/* 0x08 Command Register */
	u32 mdsr;		/* 0x0C Status Register */
	u32 mdisr;		/* 0x10 Interrupt Status Register */
	u32 mdimr;		/* 0x14 Interrupt Mask Register */
	u32 mddsr;		/* 0x1C Data Size Register */
	u32 mdin;		/* 0x20 Input FIFO */
	u32 res1[3];		/* 0x24 - 0x2F */
	u32 mdao;		/* 0x30 Message Digest AO Register */
	u32 mdbo;		/* 0x34 Message Digest BO Register */
	u32 mdco;		/* 0x38 Message Digest CO Register */
	u32 mddo;		/* 0x3C Message Digest DO Register */
	u32 mdeo;		/* 0x40 Message Digest EO Register */
	u32 mdmds;		/* 0x44 Message Data Size Register */
	u32 res[10];		/* 0x48 - 0x6F */
	u32 mda1;		/* 0x70 Message Digest A1 Register */
	u32 mdb1;		/* 0x74 Message Digest B1 Register */
	u32 mdc1;		/* 0x78 Message Digest C1 Register */
	u32 mdd1;		/* 0x7C Message Digest D1 Register */
	u32 mde1;		/* 0x80 Message Digest E1 Register */
} mdha_t;

/* Symmetric Key Hardware Accelerator */
typedef struct skha_ctrl {
	u32 mr;			/* 0x00 Mode Register */
	u32 cr;			/* 0x04 Control Register */
	u32 cmr;		/* 0x08 Command Register */
	u32 sr;			/* 0x0C Status Register */
	u32 esr;		/* 0x10 Error Status Register */
	u32 emr;		/* 0x14 Error Status Mask Register) */
	u32 ksr;		/* 0x18 Key Size Register */
	u32 dsr;		/* 0x1C Data Size Register */
	u32 in;			/* 0x20 Input FIFO */
	u32 out;		/* 0x24 Output FIFO */
	u32 res1[2];		/* 0x28 - 0x2F */
	u32 kdr1;		/* 0x30 Key Data Register 1  */
	u32 kdr2;		/* 0x34 Key Data Register 2 */
	u32 kdr3;		/* 0x38 Key Data Register 3 */
	u32 kdr4;		/* 0x3C Key Data Register 4 */
	u32 kdr5;		/* 0x40 Key Data Register 5 */
	u32 kdr6;		/* 0x44 Key Data Register 6 */
	u32 res2[10];		/* 0x48 - 0x6F */
	u32 c1;			/* 0x70 Context 1 */
	u32 c2;			/* 0x74 Context 2 */
	u32 c3;			/* 0x78 Context 3 */
	u32 c4;			/* 0x7C Context 4 */
	u32 c5;			/* 0x80 Context 5 */
	u32 c6;			/* 0x84 Context 6 */
	u32 c7;			/* 0x88 Context 7 */
	u32 c8;			/* 0x8C Context 8 */
	u32 c9;			/* 0x90 Context 9 */
	u32 c10;		/* 0x94 Context 10 */
	u32 c11;		/* 0x98 Context 11 */
} skha_t;

/* Random Number Generator */
typedef struct rng_ctrl {
	u32 rngcr;		/* 0x00 RNG Control Register */
	u32 rngsr;		/* 0x04 RNG Status Register */
	u32 rnger;		/* 0x08 RNG Entropy Register */
	u32 rngout;		/* 0x0C RNG Output FIFO */
} rng_t;

/* System control module registers 2 */
typedef struct scm2_ctrl {
	u32 mpr1;		/* 0x00 Master Privilege Register */
	u32 res1[7];		/* 0x04 - 0x1F */
	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
	u32 res2[4];		/* 0x30 - 0x3F */
	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
	u32 res3[2];		/* 0x4C - 0x53 */
	u32 bmt1;		/* 0x54 Bus Monitor Timeout 1 */
} scm2_t;

/* Cross-Bar Switch Module */
typedef struct xbs_ctrl {
	u32 prs1;		/* 0x100 Priority Register Slave 1 */
	u32 res1[3];		/* 0x104 - 0F */
	u32 crs1;		/* 0x110 Control Register Slave 1 */
	u32 res2[187];		/* 0x114 - 0x3FF */

	u32 prs4;		/* 0x400 Priority Register Slave 4 */
	u32 res3[3];		/* 0x404 - 0F */
	u32 crs4;		/* 0x410 Control Register Slave 4 */
	u32 res4[123];		/* 0x414 - 0x5FF */

	u32 prs6;		/* 0x600 Priority Register Slave 6 */
	u32 res5[3];		/* 0x604 - 0F */
	u32 crs6;		/* 0x610 Control Register Slave 6 */
	u32 res6[59];		/* 0x614 - 0x6FF */

	u32 prs7;		/* 0x700 Priority Register Slave 7 */
	u32 res7[3];		/* 0x704 - 0F */
	u32 crs7;		/* 0x710 Control Register Slave 7 */
} xbs_t;

/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
	u16 res0;
	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
	u32 cscr0;		/* 0x08 Chip-Select Control Register 0 */

	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
	u16 res1;
	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
	u32 cscr1;		/* 0x14 Chip-Select Control Register 1 */

	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
	u16 res2;
	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
	u32 cscr2;		/* 0x20 Chip-Select Control Register 2 */

	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
	u16 res3;
	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
	u32 cscr3;		/* 0x2C Chip-Select Control Register 3 */

	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
	u16 res4;
	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
	u32 cscr4;		/* 0x38 Chip-Select Control Register 4 */

	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
	u16 res5;
	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
	u32 cscr5;		/* 0x44 Chip-Select Control Register 5 */
} fbcs_t;

/* FlexCan module registers */
typedef struct can_ctrl {
	u32 mcr;		/* 0x00 Module Configuration register */
	u32 ctrl;		/* 0x04 Control register */
	u32 timer;		/* 0x08 Free Running Timer */
	u32 res1;		/* 0x0C */
	u32 rxgmask;		/* 0x10 Rx Global Mask */
	u32 rx14mask;		/* 0x14 RxBuffer 14 Mask */
	u32 rx15mask;		/* 0x18 RxBuffer 15 Mask */
	u32 errcnt;		/* 0x1C Error Counter Register */
	u32 errstat;		/* 0x20 Error and status Register */
	u32 res2;		/* 0x24 */
	u32 imask;		/* 0x28 Interrupt Mask Register */
	u32 res3;		/* 0x2C */
	u32 iflag;		/* 0x30 Interrupt Flag Register */
	u32 res4[19];		/* 0x34 - 0x7F */
	u32 MB0_15[2048];	/* 0x80 Message Buffer 0-15 */
} can_t;

/* System Control Module register 3 */
typedef struct scm3_ctrl {
	u8 res1[19];		/* 0x00 - 0x12 */
	u8 wcr;			/* 0x13 wakeup control register */
	u16 res2;		/* 0x14 - 0x15 */
	u16 cwcr;		/* 0x16 Core Watchdog Control Register */
	u8 res3[3];		/* 0x18 - 0x1A */
	u8 cwsr;		/* 0x1B Core Watchdog Service Register */
	u8 res4[2];		/* 0x1C - 0x1D */
	u8 scmisr;		/* 0x1F Interrupt Status Register */
	u32 res5;		/* 0x20 */
	u32 bcr;		/* 0x24 Burst Configuration Register */
	u32 res6[18];		/* 0x28 - 0x6F */
	u32 cfadr;		/* 0x70 Core Fault Address Register */
	u8 res7[4];		/* 0x71 - 0x74 */
	u8 cfier;		/* 0x75 Core Fault Interrupt Enable Register */
	u8 cfloc;		/* 0x76 Core Fault Location Register */
	u8 cfatr;		/* 0x77 Core Fault Attributes Register */
	u32 res8;		/* 0x78 */
	u32 cfdtr;		/* 0x7C Core Fault Data Register */
} scm3_t;

/* eDMA module registers */
typedef struct edma_ctrl {
	u32 cr;			/* 0x00 Control Register */
	u32 es;			/* 0x04 Error Status Register */
	u16 res1[3];		/* 0x08 - 0x0D */
	u16 erq;		/* 0x0E Enable Request Register */
	u16 res2[3];		/* 0x10 - 0x15 */
	u16 eei;		/* 0x16 Enable Error Interrupt Request */
	u8 serq;		/* 0x18 Set Enable Request */
	u8 cerq;		/* 0x19 Clear Enable Request */
	u8 seei;		/* 0x1A Set Enable Error Interrupt Request */
	u8 ceei;		/* 0x1B Clear Enable Error Interrupt Request */
	u8 cint;		/* 0x1C Clear Interrupt Enable Register */
	u8 cerr;		/* 0x1D Clear Error Register */
	u8 ssrt;		/* 0x1E Set START Bit Register */
	u8 cdne;		/* 0x1F Clear DONE Status Bit Register */
	u16 res3[3];		/* 0x20 - 0x25 */
	u16 intr;		/* 0x26 Interrupt Request Register */
	u16 res4[3];		/* 0x28 - 0x2D */
	u16 err;		/* 0x2E Error Register */
	u32 res5[52];		/* 0x30 - 0xFF */
	u8 dchpri0;		/* 0x100 Channel 0 Priority Register */
	u8 dchpri1;		/* 0x101 Channel 1 Priority Register */
	u8 dchpri2;		/* 0x102 Channel 2 Priority Register */
	u8 dchpri3;		/* 0x103 Channel 3 Priority Register */
	u8 dchpri4;		/* 0x104 Channel 4 Priority Register */
	u8 dchpri5;		/* 0x105 Channel 5 Priority Register */
	u8 dchpri6;		/* 0x106 Channel 6 Priority Register */
	u8 dchpri7;		/* 0x107 Channel 7 Priority Register */
	u8 dchpri8;		/* 0x108 Channel 8 Priority Register */
	u8 dchpri9;		/* 0x109 Channel 9 Priority Register */
	u8 dchpri10;		/* 0x110 Channel 10 Priority Register */
	u8 dchpri11;		/* 0x111 Channel 11 Priority Register */
	u8 dchpri12;		/* 0x112 Channel 12 Priority Register */
	u8 dchpri13;		/* 0x113 Channel 13 Priority Register */
	u8 dchpri14;		/* 0x114 Channel 14 Priority Register */
	u8 dchpri15;		/* 0x115 Channel 15 Priority Register */
} edma_t;

/* TCD - eDMA*/
typedef struct tcd_ctrl {
	u32 saddr;		/* 0x00 Source Address */
	u16 attr;		/* 0x04 Transfer Attributes */
	u16 soff;		/* 0x06 Signed Source Address Offset */
	u32 nbytes;		/* 0x08 Minor Byte Count */
	u32 slast;		/* 0x0C Last Source Address Adjustment */
	u32 daddr;		/* 0x10 Destination address */
	u16 citer;		/* 0x14 Current Minor Loop Link, Major Loop Count */
	u16 doff;		/* 0x16 Signed Destination Address Offset */
	u32 dlast_sga;		/* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
	u16 biter;		/* 0x1C Beginning Minor Loop Link, Major Loop Count */
	u16 csr;		/* 0x1E Control and Status */
} tcd_st;

typedef struct tcd_multiple {
	tcd_st tcd[16];
} tcd_t;

/* Interrupt module registers */
typedef struct int0_ctrl {
	/* Interrupt Controller 0 */
	u32 iprh0;		/* 0x00 Pending Register High */
	u32 iprl0;		/* 0x04 Pending Register Low */
	u32 imrh0;		/* 0x08 Mask Register High */
	u32 imrl0;		/* 0x0C Mask Register Low */
	u32 frch0;		/* 0x10 Force Register High */
	u32 frcl0;		/* 0x14 Force Register Low */
	u16 res1;		/* 0x18 - 0x19 */
	u16 icfg0;		/* 0x1A Configuration Register */
	u8 simr0;		/* 0x1C Set Interrupt Mask */
	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
	u8 clmask0;		/* 0x1E Current Level Mask */
	u8 slmask;		/* 0x1F Saved Level Mask */
	u32 res2[8];		/* 0x20 - 0x3F */
	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
	u32 res3[24];		/* 0x80 - 0xDF */
	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
	u8 res4[3];		/* 0xE1 - 0xE3 */
	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
	u8 res5[3];		/* 0xE5 - 0xE7 */
	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
	u8 res6[3];		/* 0xE9 - 0xEB */
	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
	u8 res7[3];		/* 0xED - 0xEF */
	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
	u8 res8[3];		/* 0xF1 - 0xF3 */
	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
	u8 res9[3];		/* 0xF5 - 0xF7 */
	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
	u8 resa[3];		/* 0xF9 - 0xFB */
	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
	u8 resb[3];		/* 0xFD - 0xFF */
} int0_t;

typedef struct int1_ctrl {
	/* Interrupt Controller 1 */
	u32 iprh1;		/* 0x00 Pending Register High */
	u32 iprl1;		/* 0x04 Pending Register Low */
	u32 imrh1;		/* 0x08 Mask Register High */
	u32 imrl1;		/* 0x0C Mask Register Low */
	u32 frch1;		/* 0x10 Force Register High */
	u32 frcl1;		/* 0x14 Force Register Low */
	u16 res1;		/* 0x18 */
	u16 icfg1;		/* 0x1A Configuration Register */
	u8 simr1;		/* 0x1C Set Interrupt Mask */
	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
	u16 res2;		/* 0x1E - 0x1F */
	u32 res3[8];		/* 0x20 - 0x3F */
	u8 icr1[64];		/* 0x40 - 0x7F */
	u32 res4[24];		/* 0x80 - 0xDF */
	u8 swiack1;		/* 0xE0 Software Interrupt Acknowledge */
	u8 res5[3];		/* 0xE1 - 0xE3 */
	u8 Lniack1_1;		/* 0xE4 Level n interrupt acknowledge resister */
	u8 res6[3];		/* 0xE5 - 0xE7 */
	u8 Lniack1_2;		/* 0xE8 Level n interrupt acknowledge resister */
	u8 res7[3];		/* 0xE9 - 0xEB */
	u8 Lniack1_3;		/* 0xEC Level n interrupt acknowledge resister */
	u8 res8[3];		/* 0xED - 0xEF */
	u8 Lniack1_4;		/* 0xF0 Level n interrupt acknowledge resister */
	u8 res9[3];		/* 0xF1 - 0xF3 */
	u8 Lniack1_5;		/* 0xF4 Level n interrupt acknowledge resister */
	u8 resa[3];		/* 0xF5 - 0xF7 */
	u8 Lniack1_6;		/* 0xF8 Level n interrupt acknowledge resister */
	u8 resb[3];		/* 0xF9 - 0xFB */
	u8 Lniack1_7;		/* 0xFC Level n interrupt acknowledge resister */
	u8 resc[3];		/* 0xFD - 0xFF */
} int1_t;

typedef struct intgack_ctrl1 {
	/* Global IACK Registers */
	u8 swiack;		/* 0xE0 Global Software Interrupt Acknowledge */
	u8 Lniack[7];		/* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;

/*I2C module registers */
typedef struct i2c_ctrl {
	u8 adr;			/* 0x00 address register */
	u8 res1[3];		/* 0x01 - 0x03 */
	u8 fdr;			/* 0x04 frequency divider register */
	u8 res2[3];		/* 0x05 - 0x07 */
	u8 cr;			/* 0x08 control register */
	u8 res3[3];		/* 0x09 - 0x0B */