m5282.h

U-boot源码 ARM7启动代码

/*
 * mcf5282.h -- Definitions for Motorola Coldfire 5282
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/****************************************************************************/
#ifndef	m5282_h
#define	m5282_h

/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_LOLRE			(0x8000)
#define PLL_SYNCR_MFD2			(0x4000)
#define PLL_SYNCR_MFD1			(0x2000)
#define PLL_SYNCR_MFD0			(0x1000)
#define PLL_SYNCR_LOCRE			(0x0800)
#define PLL_SYNCR_RFC2			(0x0400)
#define PLL_SYNCR_RFC1			(0x0200)
#define PLL_SYNCR_RFC0			(0x0100)
#define PLL_SYNCR_LOCEN			(0x0080)
#define PLL_SYNCR_DISCLK		(0x0040)
#define PLL_SYNCR_FWKUP			(0x0020)
#define PLL_SYNCR_STPMD1		(0x0008)
#define PLL_SYNCR_STPMD0		(0x0004)

/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_MODE			(0x0080)
#define PLL_SYNSR_PLLSEL		(0x0040)
#define PLL_SYNSR_PLLREF		(0x0020)
#define PLL_SYNSR_LOCKS			(0x0010)
#define PLL_SYNSR_LOCK			(0x0008)
#define PLL_SYNSR_LOCS			(0x0004)

/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0			(0)
#define INT0_LO_EPORT1			(1)
#define INT0_LO_EPORT2			(2)
#define INT0_LO_EPORT3			(3)
#define INT0_LO_EPORT4			(4)
#define INT0_LO_EPORT5			(5)
#define INT0_LO_EPORT6			(6)
#define INT0_LO_EPORT7			(7)
#define INT0_LO_SCM_SWT1		(8)
#define INT0_LO_DMA_00			(9)
#define INT0_LO_DMA_01			(10)
#define INT0_LO_DMA_02			(11)
#define INT0_LO_DMA_03			(12)
#define INT0_LO_UART0			(13)
#define INT0_LO_UART1			(14)
#define INT0_LO_UART2			(15)
#define INT0_LO_RSVD1			(16)
#define INT0_LO_I2C			(17)
#define INT0_LO_QSPI			(18)
#define INT0_LO_DTMR0			(19)
#define INT0_LO_DTMR1			(20)
#define INT0_LO_DTMR2			(21)
#define INT0_LO_DTMR3			(22)
#define INT0_LO_FEC_TXF			(23)
#define INT0_LO_FEC_TXB			(24)
#define INT0_LO_FEC_UN			(25)
#define INT0_LO_FEC_RL			(26)
#define INT0_LO_FEC_RXF			(27)
#define INT0_LO_FEC_RXB			(28)
#define INT0_LO_FEC_MII			(29)
#define INT0_LO_FEC_LC			(30)
#define INT0_LO_FEC_HBERR		(31)
#define INT0_HI_FEC_GRA			(32)
#define INT0_HI_FEC_EBERR		(33)
#define INT0_HI_FEC_BABT		(34)
#define INT0_HI_FEC_BABR		(35)
#define INT0_HI_PMM_LVDF		(36)
#define INT0_HI_QADC_CF1		(37)
#define INT0_HI_QADC_CF2		(38)
#define INT0_HI_QADC_PF1		(39)
#define INT0_HI_QADC_PF2		(40)
#define INT0_HI_GPTA_TOF		(41)
#define INT0_HI_GPTA_PAIF		(42)
#define INT0_HI_GPTA_PAOVF		(43)
#define INT0_HI_GPTA_C0F		(44)
#define INT0_HI_GPTA_C1F		(45)
#define INT0_HI_GPTA_C2F		(46)
#define INT0_HI_GPTA_C3F		(47)
#define INT0_HI_GPTB_TOF		(48)
#define INT0_HI_GPTB_PAIF		(49)
#define INT0_HI_GPTB_PAOVF		(50)
#define INT0_HI_GPTB_C0F		(51)
#define INT0_HI_GPTB_C1F		(52)
#define INT0_HI_GPTB_C2F		(53)
#define INT0_HI_GPTB_C3F		(54)
#define INT0_HI_PIT0			(55)
#define INT0_HI_PIT1			(56)
#define INT0_HI_PIT2			(57)
#define INT0_HI_PIT3			(58)
#define INT0_HI_CFM_CBEIF		(59)
#define INT0_HI_CFM_CCIF		(60)
#define INT0_HI_CFM_PVIF		(61)
#define INT0_HI_CFM_AEIF		(62)

/*
 * Size of internal RAM
 */

#define INT_RAM_SIZE	65536

/* General Purpose I/O Module GPIO */

#define MCFGPIO_PORTA		(*(vu_char *) (CFG_MBAR+0x100000))
#define MCFGPIO_PORTB		(*(vu_char *) (CFG_MBAR+0x100001))
#define MCFGPIO_PORTC		(*(vu_char *) (CFG_MBAR+0x100002))
#define MCFGPIO_PORTD		(*(vu_char *) (CFG_MBAR+0x100003))
#define MCFGPIO_PORTE		(*(vu_char *) (CFG_MBAR+0x100004))
#define MCFGPIO_PORTF		(*(vu_char *) (CFG_MBAR+0x100005))
#define MCFGPIO_PORTG		(*(vu_char *) (CFG_MBAR+0x100006))
#define MCFGPIO_PORTH		(*(vu_char *) (CFG_MBAR+0x100007))
#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_MBAR+0x100008))
#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_MBAR+0x100009))
#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_MBAR+0x10000A))
#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_MBAR+0x10000B))
#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_MBAR+0x10000C))
#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_MBAR+0x10000D))
#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_MBAR+0x10000E))
#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_MBAR+0x10000F))
#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_MBAR+0x100010))
#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_MBAR+0x100011))

#define MCFGPIO_DDRA		(*(vu_char *) (CFG_MBAR+0x100014))
#define MCFGPIO_DDRB		(*(vu_char *) (CFG_MBAR+0x100015))
#define MCFGPIO_DDRC		(*(vu_char *) (CFG_MBAR+0x100016))
#define MCFGPIO_DDRD		(*(vu_char *) (CFG_MBAR+0x100017))
#define MCFGPIO_DDRE		(*(vu_char *) (CFG_MBAR+0x100018))
#define MCFGPIO_DDRF		(*(vu_char *) (CFG_MBAR+0x100019))
#define MCFGPIO_DDRG		(*(vu_char *) (CFG_MBAR+0x10001A))
#define MCFGPIO_DDRH		(*(vu_char *) (CFG_MBAR+0x10001B))
#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_MBAR+0x10001C))
#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_MBAR+0x10001D))
#define MCFGPIO_DDREH		(*(vu_char *) (CFG_MBAR+0x10001E))
#define MCFGPIO_DDREL		(*(vu_char *) (CFG_MBAR+0x10001F))
#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_MBAR+0x100020))
#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_MBAR+0x100021))
#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_MBAR+0x100022))
#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_MBAR+0x100023))
#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_MBAR+0x100024))
#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_MBAR+0x100025))

#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_MBAR+0x100039))

#define MCFGPIO_SETA		(*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_SETB		(*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_SETC		(*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_SETD		(*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE		(*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF		(*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_SETG		(*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH		(*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ		(*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD		(*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH		(*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL		(*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS		(*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS		(*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD		(*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC		(*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD		(*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA		(*(vu_char *) (CFG_MBAR+0x100039))

#define MCFGPIO_CLRA		(*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB		(*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC		(*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD		(*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE		(*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF		(*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG		(*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH		(*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ		(*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD		(*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH		(*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL		(*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS		(*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS		(*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD		(*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC		(*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD		(*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA		(*(vu_char *) (CFG_MBAR+0x10004D))

#define MCFGPIO_PBCDPAR	(*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR		(*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR		(*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR		(*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR		(*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR		(*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR		(*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR		(*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR		(*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR		(*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR		(*(vu_char *) (CFG_MBAR+0x10005C))

/* Bit level definitions and macros */
#define MCFGPIO_PORT7			(0x80)
#define MCFGPIO_PORT6			(0x40)
#define MCFGPIO_PORT5			(0x20)
#define MCFGPIO_PORT4			(0x10)
#define MCFGPIO_PORT3			(0x08)
#define MCFGPIO_PORT2			(0x04)
#define MCFGPIO_PORT1			(0x02)
#define MCFGPIO_PORT0			(0x01)
#define MCFGPIO_PORT(x)			(0x01<<x)

#define MCFGPIO_DDR7			(0x80)
#define MCFGPIO_DDR6			(0x40)
#define MCFGPIO_DDR5			(0x20)
#define MCFGPIO_DDR4			(0x10)
#define MCFGPIO_DDR3			(0x08)
#define MCFGPIO_DDR2			(0x04)
#define MCFGPIO_DDR1			(0x02)
#define MCFGPIO_DDR0			(0x01)
#define MCFGPIO_DDR(x)			(0x01<<x)

#define MCFGPIO_Px7			(0x80)
#define MCFGPIO_Px6			(0x40)
#define MCFGPIO_Px5			(0x20)
#define MCFGPIO_Px4			(0x10)
#define MCFGPIO_Px3			(0x08)
#define MCFGPIO_Px2			(0x04)
#define MCFGPIO_Px1			(0x02)
#define MCFGPIO_Px0			(0x01)
#define MCFGPIO_Px(x)			(0x01<<x)

#define MCFGPIO_PBCDPAR_PBPA		(0x80)
#define MCFGPIO_PBCDPAR_PCDPA		(0x40)

#define MCFGPIO_PEPAR_PEPA7		(0x4000)
#define MCFGPIO_PEPAR_PEPA6		(0x1000)
#define MCFGPIO_PEPAR_PEPA5		(0x0400)
#define MCFGPIO_PEPAR_PEPA4		(0x0100)
#define MCFGPIO_PEPAR_PEPA3		(0x0040)
#define MCFGPIO_PEPAR_PEPA2		(0x0010)
#define MCFGPIO_PEPAR_PEPA1(x)		(((x)&0x3)<<2)
#define MCFGPIO_PEPAR_PEPA0(x)		(((x)&0x3))

#define MCFGPIO_PFPAR_PFPA7		(0x80)
#define MCFGPIO_PFPAR_PFPA6		(0x40)
#define MCFGPIO_PFPAR_PFPA5		(0x20)

#define MCFGPIO_PJPAR_PJPA7		(0x80)
#define MCFGPIO_PJPAR_PJPA6		(0x40)
#define MCFGPIO_PJPAR_PJPA5		(0x20)
#define MCFGPIO_PJPAR_PJPA4		(0x10)
#define MCFGPIO_PJPAR_PJPA3		(0x08)
#define MCFGPIO_PJPAR_PJPA2		(0x04)
#define MCFGPIO_PJPAR_PJPA1		(0x02)
#define MCFGPIO_PJPAR_PJPA0		(0x01)
#define MCFGPIO_PJPAR_PJPA(x)		(0x01<<x)

#define MCFGPIO_PSDPAR_PSDPA		(0x80)

#define MCFGPIO_PASPAR_PASPA5(x)	(((x)&0x3)<<10)
#define MCFGPIO_PASPAR_PASPA4(x)	(((x)&0x3)<<8)
#define MCFGPIO_PASPAR_PASPA3(x)	(((x)&0x3)<<6)
#define MCFGPIO_PASPAR_PASPA2(x)	(((x)&0x3)<<4)
#define MCFGPIO_PASPAR_PASPA1(x)	(((x)&0x3)<<2)
#define MCFGPIO_PASPAR_PASPA0(x)	(((x)&0x3))

#define MCFGPIO_PEHLPAR_PEHPA		(0x80)
#define MCFGPIO_PEHLPAR_PELPA		(0x40)

#define MCFGPIO_PQSPAR_PQSPA6		(0x40)
#define MCFGPIO_PQSPAR_PQSPA5		(0x20)
#define MCFGPIO_PQSPAR_PQSPA4		(0x10)
#define MCFGPIO_PQSPAR_PQSPA3		(0x08)
#define MCFGPIO_PQSPAR_PQSPA2		(0x04)
#define MCFGPIO_PQSPAR_PQSPA1		(0x02)
#define MCFGPIO_PQSPAR_PQSPA0		(0x01)
#define MCFGPIO_PQSPAR_PQSPA(x)		(0x01<<x)

#define MCFGPIO_PTCPAR_PTCPA3(x)	(((x)&0x3)<<6)
#define MCFGPIO_PTCPAR_PTCPA2(x)	(((x)&0x3)<<4)
#define MCFGPIO_PTCPAR_PTCPA1(x)	(((x)&0x3)<<2)
#define MCFGPIO_PTCPAR_PTCPA0(x)	(((x)&0x3))