m5445x.h

U-boot源码 ARM7启动代码

/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/

/* Bit definitions and macros for SDMR */
#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
#define SDRAMC_SDMR_BK_LMR		(0x00000000)
#define SDRAMC_SDMR_BK_LEMR		(0x40000000)

/* Bit definitions and macros for SDCR */
#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)

/* Bit definitions and macros for SDCFG1 */
#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */

/* Bit definitions and macros for SDCFG2 */
#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */

/* Bit definitions and macros for SDCS group */
#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)

/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/

/* Bit definitions and macros for CR */
#define SSI_CR_SSI_EN			(0x00000001)
#define SSI_CR_TE			(0x00000002)
#define SSI_CR_RE			(0x00000004)
#define SSI_CR_NET			(0x00000008)
#define SSI_CR_SYN			(0x00000010)
#define SSI_CR_I2S(x)			(((x)&0x00000003)<<5)
#define SSI_CR_MCE			(0x00000080)
#define SSI_CR_TCH			(0x00000100)
#define SSI_CR_CIS			(0x00000200)
#define SSI_CR_I2S_NORMAL		(0x00000000)
#define SSI_CR_I2S_MASTER		(0x00000020)
#define SSI_CR_I2S_SLAVE		(0x00000040)

/* Bit definitions and macros for ISR */
#define SSI_ISR_TFE0			(0x00000001)
#define SSI_ISR_TFE1			(0x00000002)
#define SSI_ISR_RFF0			(0x00000004)
#define SSI_ISR_RFF1			(0x00000008)
#define SSI_ISR_RLS			(0x00000010)
#define SSI_ISR_TLS			(0x00000020)
#define SSI_ISR_RFS			(0x00000040)
#define SSI_ISR_TFS			(0x00000080)
#define SSI_ISR_TUE0			(0x00000100)
#define SSI_ISR_TUE1			(0x00000200)
#define SSI_ISR_ROE0			(0x00000400)
#define SSI_ISR_ROE1			(0x00000800)
#define SSI_ISR_TDE0			(0x00001000)
#define SSI_ISR_TDE1			(0x00002000)
#define SSI_ISR_RDR0			(0x00004000)
#define SSI_ISR_RDR1			(0x00008000)
#define SSI_ISR_RXT			(0x00010000)
#define SSI_ISR_CMDDU			(0x00020000)
#define SSI_ISR_CMDAU			(0x00040000)

/* Bit definitions and macros for IER */
#define SSI_IER_TFE0			(0x00000001)
#define SSI_IER_TFE1			(0x00000002)
#define SSI_IER_RFF0			(0x00000004)
#define SSI_IER_RFF1			(0x00000008)
#define SSI_IER_RLS			(0x00000010)
#define SSI_IER_TLS			(0x00000020)
#define SSI_IER_RFS			(0x00000040)
#define SSI_IER_TFS			(0x00000080)
#define SSI_IER_TUE0			(0x00000100)
#define SSI_IER_TUE1			(0x00000200)
#define SSI_IER_ROE0			(0x00000400)
#define SSI_IER_ROE1			(0x00000800)
#define SSI_IER_TDE0			(0x00001000)
#define SSI_IER_TDE1			(0x00002000)
#define SSI_IER_RDR0			(0x00004000)
#define SSI_IER_RDR1			(0x00008000)
#define SSI_IER_RXT			(0x00010000)
#define SSI_IER_CMDU			(0x00020000)
#define SSI_IER_CMDAU			(0x00040000)
#define SSI_IER_TIE			(0x00080000)
#define SSI_IER_TDMAE			(0x00100000)
#define SSI_IER_RIE			(0x00200000)
#define SSI_IER_RDMAE			(0x00400000)

/* Bit definitions and macros for TCR */
#define SSI_TCR_TEFS			(0x00000001)
#define SSI_TCR_TFSL			(0x00000002)
#define SSI_TCR_TFSI			(0x00000004)
#define SSI_TCR_TSCKP			(0x00000008)
#define SSI_TCR_TSHFD			(0x00000010)
#define SSI_TCR_TXDIR			(0x00000020)
#define SSI_TCR_TFDIR			(0x00000040)
#define SSI_TCR_TFEN0			(0x00000080)
#define SSI_TCR_TFEN1			(0x00000100)
#define SSI_TCR_TXBIT0			(0x00000200)

/* Bit definitions and macros for RCR */
#define SSI_RCR_REFS			(0x00000001)
#define SSI_RCR_RFSL			(0x00000002)
#define SSI_RCR_RFSI			(0x00000004)
#define SSI_RCR_RSCKP			(0x00000008)
#define SSI_RCR_RSHFD			(0x00000010)
#define SSI_RCR_RFEN0			(0x00000080)
#define SSI_RCR_RFEN1			(0x00000100)
#define SSI_RCR_RXBIT0			(0x00000200)
#define SSI_RCR_RXEXT			(0x00000400)

/* Bit definitions and macros for CCR */
#define SSI_CCR_PM(x)			(((x)&0x000000FF))
#define SSI_CCR_DC(x)			(((x)&0x0000001F)<<8)
#define SSI_CCR_WL(x)			(((x)&0x0000000F)<<13)
#define SSI_CCR_PSR			(0x00020000)
#define SSI_CCR_DIV2			(0x00040000)

/* Bit definitions and macros for FCSR */
#define SSI_FCSR_TFWM0(x)		(((x)&0x0000000F))
#define SSI_FCSR_RFWM0(x)		(((x)&0x0000000F)<<4)
#define SSI_FCSR_TFCNT0(x)		(((x)&0x0000000F)<<8)
#define SSI_FCSR_RFCNT0(x)		(((x)&0x0000000F)<<12)
#define SSI_FCSR_TFWM1(x)		(((x)&0x0000000F)<<16)
#define SSI_FCSR_RFWM1(x)		(((x)&0x0000000F)<<20)
#define SSI_FCSR_TFCNT1(x)		(((x)&0x0000000F)<<24)
#define SSI_FCSR_RFCNT1(x)		(((x)&0x0000000F)<<28)

/* Bit definitions and macros for ACR */
#define SSI_ACR_AC97EN			(0x00000001)
#define SSI_ACR_FV			(0x00000002)
#define SSI_ACR_TIF			(0x00000004)
#define SSI_ACR_RD			(0x00000008)
#define SSI_ACR_WR			(0x00000010)
#define SSI_ACR_FRDIV(x)		(((x)&0x0000003F)<<5)

/* Bit definitions and macros for ACADD */
#define SSI_ACADD_SSI_ACADD(x)		(((x)&0x0007FFFF))

/* Bit definitions and macros for ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x)		(((x)&0x0007FFFF))

/* Bit definitions and macros for ATAG */
#define SSI_ATAG_DDI_ATAG(x)		(((x)&0x0000FFFF))

/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/

/* Bit definitions and macros for PCR */
#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for internal bus clock frequency */
#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for Flexbus clock frequency */
#define PLL_PCR_OUTDIV4(x)		(((x)&0x0000000F)<<12)	/* Output divider for PCI clock frequency */
#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
#define PLL_PCR_PFDR_MASK		(0x000F0000)
#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
#define PLL_PCR_OUTDIV4_MASK		(0x0000F000)
#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)

/* Bit definitions and macros for PSR */
#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */

/*********************************************************************
* PCI
*********************************************************************/

/* Bit definitions and macros for SCR */
#define PCI_SCR_PE			(0x80000000)	/* Parity Error detected */
#define PCI_SCR_SE			(0x40000000)	/* System error signalled */
#define PCI_SCR_MA			(0x20000000)	/* Master aboart received */
#define PCI_SCR_TR			(0x10000000)	/* Target abort received */
#define PCI_SCR_TS			(0x08000000)	/* Target abort signalled */
#define PCI_SCR_DT			(0x06000000)	/* PCI_DEVSEL timing */
#define PCI_SCR_DP			(0x01000000)	/* Master data parity err */
#define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
#define PCI_SCR_R			(0x00400000)	/* Reserved */
#define PCI_SCR_66M			(0x00200000)	/* 66Mhz */
#define PCI_SCR_C			(0x00100000)	/* Capabilities list */
#define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
#define PCI_SCR_S			(0x00000100)	/* SERR enable */
#define PCI_SCR_ST			(0x00000080)	/* Addr and Data stepping */
#define PCI_SCR_PER			(0x00000040)	/* Parity error response */
#define PCI_SCR_V			(0x00000020)	/* VGA palette snoop enable */
#define PCI_SCR_MW			(0x00000010)	/* Memory write and invalidate enable */
#define PCI_SCR_SP			(0x00000008)	/* Special cycle monitor or ignore */
#define PCI_SCR_B			(0x00000004)	/* Bus master enable */
#define PCI_SCR_M			(0x00000002)	/* Memory access control */
#define PCI_SCR_IO			(0x00000001)	/* I/O access control */

#define PCI_CR1_BIST(x)			((x & 0xFF) << 24)	/* Built in self test */
#define PCI_CR1_HDR(x)			((x & 0xFF) << 16)	/* Header type */
#define PCI_CR1_LTMR(x)			((x & 0xF8) << 8)	/* Latency timer */
#define PCI_CR1_CLS(x)			(x & 0x0F)	/* Cache line size */

#define PCI_BAR_BAR0(x)			(x & 0xFFFC0000)
#define PCI_BAR_BAR1(x)			(x & 0xFFF00000)
#define PCI_BAR_BAR2(x)			(x & 0xFFC00000)
#define PCI_BAR_BAR3(x)			(x & 0xFF000000)
#define PCI_BAR_BAR4(x)			(x & 0xF8000000)
#define PCI_BAR_BAR5(x)			(x & 0xE0000000)
#define PCI_BAR_PREF			(0x00000004)	/* Prefetchable access */
#define PCI_BAR_RANGE			(0x00000002)	/* Fixed to 00 */
#define PCI_BAR_IO_M			(0x00000001)	/* IO / memory space */

#define PCI_CR2_MAXLAT(x)		((x & 0xFF) << 24)	/* Maximum latency */
#define PCI_CR2_MINGNT(x)		((x & 0xFF) << 16)	/* Minimum grant */
#define PCI_CR2_INTPIN(x)		((x & 0xFF) << 8)	/* Interrupt Pin */
#define PCI_CR2_INTLIN(x)		(x & 0xFF)	/* Interrupt Line */

#define PCI_GSCR_DRD			(0x80000000)	/* Delayed read discarded */
#define PCI_GSCR_PE			(0x20000000)	/* PCI_PERR detected */
#define PCI_GSCR_SE			(0x10000000)	/* SERR detected */
#define PCI_GSCR_ER			(0x08000000)	/* Error response detected */
#define PCI_GSCR_DRDE			(0x00008000)	/* Delayed read discarded enable */
#define PCI_GSCR_PEE			(0x00002000)	/* PERR detected interrupt enable */
#define PCI_GSCR_SEE			(0x00001000)	/* SERR detected interrupt enable */
#define PCI_GSCR_PR			(0x00000001)	/* PCI reset */

#define PCI_TCR1_LD			(0x01000000)	/* Latency rule disable */
#define PCI_TCR1_PID			(0x00020000)	/* Prefetch invalidate and disable */
#define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
#define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */

#define PCI_TCR1_B5E			(0x00002000)	/*  */
#define PCI_TCR1_B4E			(0x00001000)	/*  */
#define PCI_TCR1_B3E			(0x00000800)	/*  */
#define PCI_TCR1_B2E			(0x00000400)	/*  */
#define PCI_TCR1_B1E			(0x00000200)	/*  */
#define PCI_TCR1_B0E			(0x00000100)	/*  */
#define PCI_TCR1_CR			(0x00000001)	/*  */

#define PCI_TBATR_BAT(x)		((x & 0xFFF) << 20)
#define PCI_TBATR_EN			(0x00000001)	/* Enable */

#define PCI_IWCR_W0C_IO			(0x08000000)	/* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL		(0x04000000)	/* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN		(0x02000000)	/* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD		(0x00000000)	/* PCI Memory Read */
#define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
#define PCI_IWCR_W1C_IO			(0x00080000)	/* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL		(0x00040000)	/* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN		(0x00020000)	/* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD		(0x00000000)	/* PCI Memory Read */
#define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
#define PCI_IWCR_W2C_IO			(0x00000800)	/* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL		(0x00000400)	/* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN		(0x00000200)	/* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD		(0x00000000)	/* PCI Memory Read */
#define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */

#define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
#define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
#define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */

#define PCI_IDR_DEVID			(

/********************************************************************/

#endif				/* __MCF5445X__ */