📄 m5445x.h

📁 U-boot源码 ARM7启动代码
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#define GPIO_PAR_UART_U0TXD		(0x01)#define GPIO_PAR_UART_U0RXD		(0x02)#define GPIO_PAR_UART_U0RTS		(0x04)#define GPIO_PAR_UART_U0CTS		(0x08)#define GPIO_PAR_UART_U1TXD		(0x10)#define GPIO_PAR_UART_U1RXD		(0x20)#define GPIO_PAR_UART_U1RTS		(0x40)#define GPIO_PAR_UART_U1CTS		(0x80)#define GPIO_PAR_UART_U1CTS_U1CTS	(0x80)#define GPIO_PAR_UART_U1CTS_GPIO	(0x00)#define GPIO_PAR_UART_U1RTS_U1RTS	(0x40)#define GPIO_PAR_UART_U1RTS_GPIO	(0x00)#define GPIO_PAR_UART_U1RXD_U1RXD	(0x20)#define GPIO_PAR_UART_U1RXD_GPIO	(0x00)#define GPIO_PAR_UART_U1TXD_U1TXD	(0x10)#define GPIO_PAR_UART_U1TXD_GPIO	(0x00)#define GPIO_PAR_UART_U0CTS_U0CTS	(0x08)#define GPIO_PAR_UART_U0CTS_GPIO	(0x00)#define GPIO_PAR_UART_U0RTS_U0RTS	(0x04)#define GPIO_PAR_UART_U0RTS_GPIO	(0x00)#define GPIO_PAR_UART_U0RXD_U0RXD	(0x02)#define GPIO_PAR_UART_U0RXD_GPIO	(0x00)#define GPIO_PAR_UART_U0TXD_U0TXD	(0x01)#define GPIO_PAR_UART_U0TXD_GPIO	(0x00)/* Bit definitions and macros for PAR_FECI2C */#define GPIO_PAR_FECI2C_SDA(x)		(((x)&0x0003))#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x0003)<<2)#define GPIO_PAR_FECI2C_MDIO0		(0x0010)#define GPIO_PAR_FECI2C_MDC0		(0x0040)#define GPIO_PAR_FECI2C_MDIO1(x)	(((x)&0x0003)<<8)#define GPIO_PAR_FECI2C_MDC1(x)		(((x)&0x0003)<<10)#define GPIO_PAR_FECI2C_MDC1_MASK	(0xF3FF)#define GPIO_PAR_FECI2C_MDC1_MDC1	(0x0C00)#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR	(0x0800)#define GPIO_PAR_FECI2C_MDC1_GPIO	(0x0000)#define GPIO_PAR_FECI2C_MDIO1_MASK	(0xFCFF)#define GPIO_PAR_FECI2C_MDIO1_MDIO1	(0x0300)#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW	(0x0200)#define GPIO_PAR_FECI2C_MDIO1_GPIO	(0x0000)#define GPIO_PAR_FECI2C_MDC0_MDC0	(0x0040)#define GPIO_PAR_FECI2C_MDC0_GPIO	(0x0000)#define GPIO_PAR_FECI2C_MDIO0_MDIO0	(0x0010)#define GPIO_PAR_FECI2C_MDIO0_GPIO	(0x0000)#define GPIO_PAR_FECI2C_SCL_MASK	(0xFFF3)#define GPIO_PAR_FECI2C_SCL_SCL		(0x000C)#define GPIO_PAR_FECI2C_SCL_U2TXD	(0x0004)#define GPIO_PAR_FECI2C_SCL_GPIO	(0x0000)#define GPIO_PAR_FECI2C_SDA_MASK	(0xFFFC)#define GPIO_PAR_FECI2C_SDA_SDA		(0x0003)#define GPIO_PAR_FECI2C_SDA_U2RXD	(0x0001)#define GPIO_PAR_FECI2C_SDA_GPIO	(0x0000)/* Bit definitions and macros for PAR_SSI */#define GPIO_PAR_SSI_MCLK		(0x0001)#define GPIO_PAR_SSI_STXD(x)		(((x)&0x0003)<<2)#define GPIO_PAR_SSI_SRXD(x)		(((x)&0x0003)<<4)#define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<6)#define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<8)#define GPIO_PAR_SSI_BCLK_MASK		(0xFCFF)#define GPIO_PAR_SSI_BCLK_BCLK		(0x0300)#define GPIO_PAR_SSI_BCLK_U1CTS		(0x0200)#define GPIO_PAR_SSI_BCLK_GPIO		(0x0000)#define GPIO_PAR_SSI_FS_MASK		(0xFF3F)#define GPIO_PAR_SSI_FS_FS		(0x00C0)#define GPIO_PAR_SSI_FS_U1RTS		(0x0080)#define GPIO_PAR_SSI_FS_GPIO		(0x0000)#define GPIO_PAR_SSI_SRXD_MASK		(0xFFCF)#define GPIO_PAR_SSI_SRXD_SRXD		(0x0030)#define GPIO_PAR_SSI_SRXD_U1RXD		(0x0020)#define GPIO_PAR_SSI_SRXD_GPIO		(0x0000)#define GPIO_PAR_SSI_STXD_MASK		(0xFFF3)#define GPIO_PAR_SSI_STXD_STXD		(0x000C)#define GPIO_PAR_SSI_STXD_U1TXD		(0x0008)#define GPIO_PAR_SSI_STXD_GPIO		(0x0000)#define GPIO_PAR_SSI_MCLK_MCLK		(0x0001)#define GPIO_PAR_SSI_MCLK_GPIO		(0x0000)/* Bit definitions and macros for PAR_ATA */#define GPIO_PAR_ATA_IORDY		(0x0001)#define GPIO_PAR_ATA_DMARQ		(0x0002)#define GPIO_PAR_ATA_RESET		(0x0004)#define GPIO_PAR_ATA_DA0		(0x0020)#define GPIO_PAR_ATA_DA1		(0x0040)#define GPIO_PAR_ATA_DA2		(0x0080)#define GPIO_PAR_ATA_CS0		(0x0100)#define GPIO_PAR_ATA_CS1		(0x0200)#define GPIO_PAR_ATA_BUFEN		(0x0400)#define GPIO_PAR_ATA_BUFEN_BUFEN	(0x0400)#define GPIO_PAR_ATA_BUFEN_GPIO		(0x0000)#define GPIO_PAR_ATA_CS1_CS1		(0x0200)#define GPIO_PAR_ATA_CS1_GPIO		(0x0000)#define GPIO_PAR_ATA_CS0_CS0		(0x0100)#define GPIO_PAR_ATA_CS0_GPIO		(0x0000)#define GPIO_PAR_ATA_DA2_DA2		(0x0080)#define GPIO_PAR_ATA_DA2_GPIO		(0x0000)#define GPIO_PAR_ATA_DA1_DA1		(0x0040)#define GPIO_PAR_ATA_DA1_GPIO		(0x0000)#define GPIO_PAR_ATA_DA0_DA0		(0x0020)#define GPIO_PAR_ATA_DA0_GPIO		(0x0000)#define GPIO_PAR_ATA_RESET_RESET	(0x0004)#define GPIO_PAR_ATA_RESET_GPIO		(0x0000)#define GPIO_PAR_ATA_DMARQ_DMARQ	(0x0002)#define GPIO_PAR_ATA_DMARQ_GPIO		(0x0000)#define GPIO_PAR_ATA_IORDY_IORDY	(0x0001)#define GPIO_PAR_ATA_IORDY_GPIO		(0x0000)/* Bit definitions and macros for PAR_IRQ */#define GPIO_PAR_IRQ_IRQ1		(0x02)#define GPIO_PAR_IRQ_IRQ4		(0x10)#define GPIO_PAR_IRQ_IRQ4_IRQ4		(0x10)#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)#define GPIO_PAR_IRQ_IRQ1_IRQ1		(0x02)#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)/* Bit definitions and macros for PAR_PCI */#define GPIO_PAR_PCI_REQ0		(0x0001)#define GPIO_PAR_PCI_REQ1		(0x0004)#define GPIO_PAR_PCI_REQ2		(0x0010)#define GPIO_PAR_PCI_REQ3(x)		(((x)&0x0003)<<6)#define GPIO_PAR_PCI_GNT0		(0x0100)#define GPIO_PAR_PCI_GNT1		(0x0400)#define GPIO_PAR_PCI_GNT2		(0x1000)#define GPIO_PAR_PCI_GNT3(x)		(((x)&0x0003)<<14)#define GPIO_PAR_PCI_GNT3_MASK		(0x3FFF)#define GPIO_PAR_PCI_GNT3_GNT3		(0xC000)#define GPIO_PAR_PCI_GNT3_ATA_DMACK	(0x8000)#define GPIO_PAR_PCI_GNT3_GPIO		(0x0000)#define GPIO_PAR_PCI_GNT2_GNT2		(0x1000)#define GPIO_PAR_PCI_GNT2_GPIO		(0x0000)#define GPIO_PAR_PCI_GNT1_GNT1		(0x0400)#define GPIO_PAR_PCI_GNT1_GPIO		(0x0000)#define GPIO_PAR_PCI_GNT0_GNT0		(0x0100)#define GPIO_PAR_PCI_GNT0_GPIO		(0x0000)#define GPIO_PAR_PCI_REQ3_MASK		(0xFF3F)#define GPIO_PAR_PCI_REQ3_REQ3		(0x00C0)#define GPIO_PAR_PCI_REQ3_ATA_INTRQ	(0x0080)#define GPIO_PAR_PCI_REQ3_GPIO		(0x0000)#define GPIO_PAR_PCI_REQ2_REQ2		(0x0010)#define GPIO_PAR_PCI_REQ2_GPIO		(0x0000)#define GPIO_PAR_PCI_REQ1_REQ1		(0x0040)#define GPIO_PAR_PCI_REQ1_GPIO		(0x0000)#define GPIO_PAR_PCI_REQ0_REQ0		(0x0001)#define GPIO_PAR_PCI_REQ0_GPIO		(0x0000)/* Bit definitions and macros for MSCR_SDRAM */#define GPIO_MSCR_SDRAM_SDCTL(x)	(((x)&0x03))#define GPIO_MSCR_SDRAM_SDCLK(x)	(((x)&0x03)<<2)#define GPIO_MSCR_SDRAM_SDDQS(x)	(((x)&0x03)<<4)#define GPIO_MSCR_SDRAM_SDDATA(x)	(((x)&0x03)<<6)#define GPIO_MSCR_SDRAM_SDDATA_MASK	(0x3F)#define GPIO_MSCR_SDRAM_SDDATA_DDR1	(0xC0)#define GPIO_MSCR_SDRAM_SDDATA_DDR2	(0x80)#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR	(0x40)#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR	(0x00)#define GPIO_MSCR_SDRAM_SDDQS_MASK	(0xCF)#define GPIO_MSCR_SDRAM_SDDQS_DDR1	(0x30)#define GPIO_MSCR_SDRAM_SDDQS_DDR2	(0x20)#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR	(0x10)#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR	(0x00)#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)#define GPIO_MSCR_SDRAM_SDCLK_DDR1	(0x0C)#define GPIO_MSCR_SDRAM_SDCLK_DDR2	(0x08)#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR	(0x04)#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR	(0x00)#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)#define GPIO_MSCR_SDRAM_SDCTL_DDR1	(0x03)#define GPIO_MSCR_SDRAM_SDCTL_DDR2	(0x02)#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR	(0x01)#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR	(0x00)/* Bit definitions and macros for MSCR_PCI */#define GPIO_MSCR_PCI_PCI		(0x01)#define GPIO_MSCR_PCI_PCI_HI_66MHZ	(0x01)#define GPIO_MSCR_PCI_PCI_LO_33MHZ	(0x00)/* Bit definitions and macros for DSCR_I2C */#define GPIO_DSCR_I2C_I2C(x)		(((x)&0x03))#define GPIO_DSCR_I2C_I2C_LOAD_50PF	(0x03)#define GPIO_DSCR_I2C_I2C_LOAD_30PF	(0x02)#define GPIO_DSCR_I2C_I2C_LOAD_20PF	(0x01)#define GPIO_DSCR_I2C_I2C_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_FLEXBUS */#define GPIO_DSCR_FLEXBUS_FBADL(x)		(((x)&0x03))#define GPIO_DSCR_FLEXBUS_FBADH(x)		(((x)&0x03)<<2)#define GPIO_DSCR_FLEXBUS_FBCTL(x)		(((x)&0x03)<<4)#define GPIO_DSCR_FLEXBUS_FBCLK(x)		(((x)&0x03)<<6)#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF	(0xC0)#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF	(0x80)#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF	(0x40)#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF	(0x00)#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF	(0x30)#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF	(0x20)#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF	(0x10)#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF	(0x00)#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF	(0x0C)#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF	(0x08)#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF	(0x04)#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF	(0x00)#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF	(0x03)#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF	(0x02)#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF	(0x01)#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_FEC */#define GPIO_DSCR_FEC_FEC0(x)		(((x)&0x03))#define GPIO_DSCR_FEC_FEC1(x)		(((x)&0x03)<<2)#define GPIO_DSCR_FEC_FEC1_LOAD_50PF	(0x0C)#define GPIO_DSCR_FEC_FEC1_LOAD_30PF	(0x08)#define GPIO_DSCR_FEC_FEC1_LOAD_20PF	(0x04)#define GPIO_DSCR_FEC_FEC1_LOAD_10PF	(0x00)#define GPIO_DSCR_FEC_FEC0_LOAD_50PF	(0x03)#define GPIO_DSCR_FEC_FEC0_LOAD_30PF	(0x02)#define GPIO_DSCR_FEC_FEC0_LOAD_20PF	(0x01)#define GPIO_DSCR_FEC_FEC0_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_UART */#define GPIO_DSCR_UART_UART0(x)		(((x)&0x03))#define GPIO_DSCR_UART_UART1(x)		(((x)&0x03)<<2)#define GPIO_DSCR_UART_UART1_LOAD_50PF	(0x0C)#define GPIO_DSCR_UART_UART1_LOAD_30PF	(0x08)#define GPIO_DSCR_UART_UART1_LOAD_20PF	(0x04)#define GPIO_DSCR_UART_UART1_LOAD_10PF	(0x00)#define GPIO_DSCR_UART_UART0_LOAD_50PF	(0x03)#define GPIO_DSCR_UART_UART0_LOAD_30PF	(0x02)#define GPIO_DSCR_UART_UART0_LOAD_20PF	(0x01)#define GPIO_DSCR_UART_UART0_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_DSPI */#define GPIO_DSCR_DSPI_DSPI(x)		(((x)&0x03))#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF	(0x03)#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF	(0x02)#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF	(0x01)#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_TIMER */#define GPIO_DSCR_TIMER_TIMER(x)	(((x)&0x03))#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF	(0x03)#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF	(0x02)#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF	(0x01)#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_SSI */#define GPIO_DSCR_SSI_SSI(x)		(((x)&0x03))#define GPIO_DSCR_SSI_SSI_LOAD_50PF	(0x03)#define GPIO_DSCR_SSI_SSI_LOAD_30PF	(0x02)#define GPIO_DSCR_SSI_SSI_LOAD_20PF	(0x01)#define GPIO_DSCR_SSI_SSI_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_DMA */#define GPIO_DSCR_DMA_DMA(x)		(((x)&0x03))#define GPIO_DSCR_DMA_DMA_LOAD_50PF	(0x03)#define GPIO_DSCR_DMA_DMA_LOAD_30PF	(0x02)#define GPIO_DSCR_DMA_DMA_LOAD_20PF	(0x01)#define GPIO_DSCR_DMA_DMA_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_DEBUG */#define GPIO_DSCR_DEBUG_DEBUG(x)	(((x)&0x03))#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF	(0x03)#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF	(0x02)#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF	(0x01)#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_RESET */#define GPIO_DSCR_RESET_RESET(x)	(((x)&0x03))#define GPIO_DSCR_RESET_RESET_LOAD_50PF	(0x03)#define GPIO_DSCR_RESET_RESET_LOAD_30PF	(0x02)#define GPIO_DSCR_RESET_RESET_LOAD_20PF	(0x01)#define GPIO_DSCR_RESET_RESET_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_IRQ */#define GPIO_DSCR_IRQ_IRQ(x)		(((x)&0x03))#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF	(0x03)#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF	(0x02)#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF	(0x01)#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_USB */#define GPIO_DSCR_USB_USB(x)		(((x)&0x03))#define GPIO_DSCR_USB_USB_LOAD_50PF	(0x03)#define GPIO_DSCR_USB_USB_LOAD_30PF	(0x02)#define GPIO_DSCR_USB_USB_LOAD_20PF	(0x01)#define GPIO_DSCR_USB_USB_LOAD_10PF	(0x00)/* Bit definitions and macros for DSCR_ATA */#define GPIO_DSCR_ATA_ATA(x)		(((x)&0x03))#define GPIO_DSCR_ATA_ATA_LOAD_50PF	(0x03)#define GPIO_DSCR_ATA_ATA_LOAD_30PF	(0x02)#define GPIO_DSCR_ATA_ATA_LOAD_20PF	(0x01)#define GPIO_DSCR_ATA_ATA_LOAD_10PF	(0x00)/********************************************************************** Random Number Generator (RNG)*********************************************************************//* Bit definitions and macros for RNGCR */#define RNG_RNGCR_GO			(0x00000001)#define RNG_RNGCR_HA			(0x00000002)#define RNG_RNGCR_IM			(0x00000004)#define RNG_RNGCR_CI			(0x00000008)/* Bit definitions and macros for RNGSR */#define RNG_RNGSR_SV			(0x00000001)#define RNG_RNGSR_LRS			(0x00000002)#define RNG_RNGSR_FUF			(0x00000004)#define RNG_RNGSR_EI			(0x00000008)#define RNG_RNGSR_OFL(x)		(((x)&0x000000FF)<<8)#define RNG_RNGSR_OFS(x)		(((x)&0x000000FF)<<16)
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