📄 m5445x.h

📁 U-boot源码 ARM7启动代码
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#define WTM_WCR_EN			(0x0001)#define WTM_WCR_HALTED			(0x0002)#define WTM_WCR_DOZE			(0x0004)#define WTM_WCR_WAIT			(0x0008)/********************************************************************** Serial Boot Facility (SBF)*********************************************************************//* Bit definitions and macros for SBFCR */#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))	/* Boot loader clock divider */#define SBF_SBFCR_FR			(0x0010)	/* Fast read *//********************************************************************** Reset Controller Module (RCM)*********************************************************************//* Bit definitions and macros for RCR */#define RCM_RCR_FRCRSTOUT		(0x40)#define RCM_RCR_SOFTRST			(0x80)/* Bit definitions and macros for RSR */#define RCM_RSR_LOL			(0x01)#define RCM_RSR_WDR_CORE		(0x02)#define RCM_RSR_EXT			(0x04)#define RCM_RSR_POR			(0x08)#define RCM_RSR_SOFT			(0x20)/********************************************************************** Chip Configuration Module (CCM)*********************************************************************//* Bit definitions and macros for CCR_360 */#define CCM_CCR_360_PLLMULT2(x)		(((x)&0x0003))	/* 2-Bit PLL clock mode */#define CCM_CCR_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */#define CCM_CCR_360_PCIMODE		(0x0008)	/* PCI host/agent mode */#define CCM_CCR_360_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_CCR_360_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */#define CCM_CCR_360_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL Clock Mode */#define CCM_CCR_360_OSCMODE		(0x0008)	/* Oscillator Clock Mode */#define CCM_CCR_360_FBCONFIG_MASK	(0x00E0)#define CCM_CCR_360_PLLMULT2_MASK	(0x0003)#define CCM_CCR_360_PLLMULT3_MASK	(0x0007)#define CCM_CCR_360_FBCONFIG_NM_NP_32	(0x0000)#define CCM_CCR_360_FBCONFIG_NM_NP_8	(0x0020)#define CCM_CCR_360_FBCONFIG_NM_NP_16	(0x0040)#define CCM_CCR_360_FBCONFIG_M_P_16	(0x0060)#define CCM_CCR_360_FBCONFIG_M_NP_32	(0x0080)#define CCM_CCR_360_FBCONFIG_M_NP_8	(0x00A0)#define CCM_CCR_360_FBCONFIG_M_NP_16	(0x00C0)#define CCM_CCR_360_FBCONFIG_M_P_8	(0x00E0)#define CCM_CCR_360_PLLMULT2_12X	(0x0000)#define CCM_CCR_360_PLLMULT2_6X		(0x0001)#define CCM_CCR_360_PLLMULT2_16X	(0x0002)#define CCM_CCR_360_PLLMULT2_8X		(0x0003)#define CCM_CCR_360_PLLMULT3_20X	(0x0000)#define CCM_CCR_360_PLLMULT3_10X	(0x0001)#define CCM_CCR_360_PLLMULT3_24X	(0x0002)#define CCM_CCR_360_PLLMULT3_18X	(0x0003)#define CCM_CCR_360_PLLMULT3_12X	(0x0004)#define CCM_CCR_360_PLLMULT3_6X		(0x0005)#define CCM_CCR_360_PLLMULT3_16X	(0x0006)#define CCM_CCR_360_PLLMULT3_8X		(0x0007)/* Bit definitions and macros for CCR_256 */#define CCM_CCR_256_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL clock mode */#define CCM_CCR_256_OSCMODE		(0x0008)	/* Oscillator clock mode */#define CCM_CCR_256_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_CCR_256_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */#define CCM_CCR_256_FBCONFIG_MASK	(0x00E0)#define CCM_CCR_256_FBCONFIG_NM_32	(0x0000)#define CCM_CCR_256_FBCONFIG_NM_8	(0x0020)#define CCM_CCR_256_FBCONFIG_NM_16	(0x0040)#define CCM_CCR_256_FBCONFIG_M_32	(0x0080)#define CCM_CCR_256_FBCONFIG_M_8	(0x00A0)#define CCM_CCR_256_FBCONFIG_M_16	(0x00C0)#define CCM_CCR_256_PLLMULT3_MASK	(0x0007)#define CCM_CCR_256_PLLMULT3_20X	(0x0000)#define CCM_CCR_256_PLLMULT3_10X	(0x0001)#define CCM_CCR_256_PLLMULT3_24X	(0x0002)#define CCM_CCR_256_PLLMULT3_18X	(0x0003)#define CCM_CCR_256_PLLMULT3_12X	(0x0004)#define CCM_CCR_256_PLLMULT3_6X		(0x0005)#define CCM_CCR_256_PLLMULT3_16X	(0x0006)#define CCM_CCR_256_PLLMULT3_8X		(0x0007)/* Bit definitions and macros for RCON_360 */#define CCM_RCON_360_PLLMULT(x)		(((x)&0x0003))	/* PLL clock mode */#define CCM_RCON_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */#define CCM_RCON_360_PCIMODE		(0x0008)	/* PCI host/agent mode */#define CCM_RCON_360_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_RCON_360_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration *//* Bit definitions and macros for RCON_256 */#define CCM_RCON_256_PLLMULT(x)		(((x)&0x0007))	/* PLL clock mode */#define CCM_RCON_256_OSCMODE		(0x0008)	/* Oscillator clock mode */#define CCM_RCON_256_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_RCON_256_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration *//* Bit definitions and macros for CIR */#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */#define CCM_CIR_PIN_MASK		(0xFFC0)#define CCM_CIR_PRN_MASK		(0x003F)#define CCM_CIR_PIN_MCF54450		(0x4F<<6)#define CCM_CIR_PIN_MCF54451		(0x4D<<6)#define CCM_CIR_PIN_MCF54452		(0x4B<<6)#define CCM_CIR_PIN_MCF54453		(0x49<<6)#define CCM_CIR_PIN_MCF54454		(0x4A<<6)#define CCM_CIR_PIN_MCF54455		(0x48<<6)/* Bit definitions and macros for MISCCR */#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense polarity */#define CCM_MISCCR_USBPUE		(0x0004)	/* USB transceiver pull-up enable */#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)	/* Bus monitor timing field */#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor external enable bit */#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */#define CCM_MISCCR_BMT_65536		(0)#define CCM_MISCCR_BMT_32768		(1)#define CCM_MISCCR_BMT_16384		(2)#define CCM_MISCCR_BMT_8192		(3)#define CCM_MISCCR_BMT_4096		(4)#define CCM_MISCCR_BMT_2048		(5)#define CCM_MISCCR_BMT_1024		(6)#define CCM_MISCCR_BMT_512		(7)#define CCM_MISCCR_SSIPUS_UP		(1)#define CCM_MISCCR_SSIPUS_DOWN		(0)#define CCM_MISCCR_TIMDMA_TIM		(1)#define CCM_MISCCR_TIMDMA_SSI		(0)#define CCM_MISCCR_SSISRC_CLKIN		(0)#define CCM_MISCCR_SSISRC_PLL		(1)#define CCM_MISCCR_USBOC_ACTHI		(0)#define CCM_MISCCR_USBOV_ACTLO		(1)#define CCM_MISCCR_USBSRC_CLKIN		(0)#define CCM_MISCCR_USBSRC_PLL		(1)/* Bit definitions and macros for CDR */#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clock divider */#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clock divider *//* Bit definitions and macros for UOCSR */#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down enable */#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt enable */#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */#define CCM_UOCSR_PWRFLT		(0x0008)	/* VBUS power fault */#define CCM_UOCSR_SEND			(0x0010)	/* Session end */#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (read-only) */#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor enabled (read-only) */#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (read-only) */#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (read-only) */#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (read-only) *//********************************************************************** General Purpose I/O Module (GPIO)*********************************************************************//* Bit definitions and macros for PAR_FEC */#define GPIO_PAR_FEC_FEC0(x)		(((x)&0x07))#define GPIO_PAR_FEC_FEC1(x)		(((x)&0x07)<<4)#define GPIO_PAR_FEC_FEC1_MASK		(0x8F)#define GPIO_PAR_FEC_FEC1_MII		(0x70)#define GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)#define GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)#define GPIO_PAR_FEC_FEC1_ATA		(0x10)#define GPIO_PAR_FEC_FEC1_GPIO		(0x00)#define GPIO_PAR_FEC_FEC0_MASK		(0xF8)#define GPIO_PAR_FEC_FEC0_MII		(0x07)#define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)#define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)#define GPIO_PAR_FEC_FEC0_ULPI		(0x01)#define GPIO_PAR_FEC_FEC0_GPIO		(0x00)/* Bit definitions and macros for PAR_DMA */#define GPIO_PAR_DMA_DREQ0		(0x01)#define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<2)#define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<4)#define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)#define GPIO_PAR_DMA_DACK1_MASK		(0x3F)#define GPIO_PAR_DMA_DACK1_DACK1	(0xC0)#define GPIO_PAR_DMA_DACK1_ULPI_DIR	(0x40)#define GPIO_PAR_DMA_DACK1_GPIO		(0x00)#define GPIO_PAR_DMA_DREQ1_MASK		(0xCF)#define GPIO_PAR_DMA_DREQ1_DREQ1	(0x30)#define GPIO_PAR_DMA_DREQ1_USB_CLKIN	(0x10)#define GPIO_PAR_DMA_DREQ1_GPIO		(0x00)#define GPIO_PAR_DMA_DACK0_MASK		(0xF3)#define GPIO_PAR_DMA_DACK0_DACK1	(0x0C)#define GPIO_PAR_DMA_DACK0_ULPI_DIR	(0x04)#define GPIO_PAR_DMA_DACK0_GPIO		(0x00)#define GPIO_PAR_DMA_DREQ0_DREQ0	(0x01)#define GPIO_PAR_DMA_DREQ0_GPIO		(0x00)/* Bit definitions and macros for PAR_FBCTL */#define GPIO_PAR_FBCTL_TS(x)		(((x)&0x03)<<3)#define GPIO_PAR_FBCTL_RW		(0x20)#define GPIO_PAR_FBCTL_TA		(0x40)#define GPIO_PAR_FBCTL_OE		(0x80)#define GPIO_PAR_FBCTL_OE_OE		(0x80)#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)#define GPIO_PAR_FBCTL_TA_TA		(0x40)#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)#define GPIO_PAR_FBCTL_RW_RW		(0x20)#define GPIO_PAR_FBCTL_RW_GPIO		(0x00)#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)#define GPIO_PAR_FBCTL_TS_TS		(0x18)#define GPIO_PAR_FBCTL_TS_ALE		(0x10)#define GPIO_PAR_FBCTL_TS_TBST		(0x08)#define GPIO_PAR_FBCTL_TS_GPIO		(0x80)/* Bit definitions and macros for PAR_DSPI */#define GPIO_PAR_DSPI_SCK		(0x01)#define GPIO_PAR_DSPI_SOUT		(0x02)#define GPIO_PAR_DSPI_SIN		(0x04)#define GPIO_PAR_DSPI_PCS0		(0x08)#define GPIO_PAR_DSPI_PCS1		(0x10)#define GPIO_PAR_DSPI_PCS2		(0x20)#define GPIO_PAR_DSPI_PCS5		(0x40)#define GPIO_PAR_DSPI_PCS5_PCS5		(0x40)#define GPIO_PAR_DSPI_PCS5_GPIO		(0x00)#define GPIO_PAR_DSPI_PCS2_PCS2		(0x20)#define GPIO_PAR_DSPI_PCS2_GPIO		(0x00)#define GPIO_PAR_DSPI_PCS1_PCS1		(0x10)#define GPIO_PAR_DSPI_PCS1_GPIO		(0x00)#define GPIO_PAR_DSPI_PCS0_PCS0		(0x08)#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)#define GPIO_PAR_DSPI_SIN_SIN		(0x04)#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)#define GPIO_PAR_DSPI_SOUT_SOUT		(0x02)#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)#define GPIO_PAR_DSPI_SCK_SCK		(0x01)#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)/* Bit definitions and macros for PAR_BE */#define GPIO_PAR_BE_BS0			(0x01)#define GPIO_PAR_BE_BS1			(0x04)#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)#define GPIO_PAR_BE_BE3_MASK		(0x3F)#define GPIO_PAR_BE_BE3_BE3		(0xC0)#define GPIO_PAR_BE_BE3_TSIZ1		(0x80)#define GPIO_PAR_BE_BE3_GPIO		(0x00)#define GPIO_PAR_BE_BE2_MASK		(0xCF)#define GPIO_PAR_BE_BE2_BE2		(0x30)#define GPIO_PAR_BE_BE2_TSIZ0		(0x20)#define GPIO_PAR_BE_BE2_GPIO		(0x00)#define GPIO_PAR_BE_BE1_BE1		(0x04)#define GPIO_PAR_BE_BE1_GPIO		(0x00)#define GPIO_PAR_BE_BE0_BE0		(0x01)#define GPIO_PAR_BE_BE0_GPIO		(0x00)/* Bit definitions and macros for PAR_CS */#define GPIO_PAR_CS_CS1			(0x02)#define GPIO_PAR_CS_CS2			(0x04)#define GPIO_PAR_CS_CS3			(0x08)#define GPIO_PAR_CS_CS3_CS3		(0x08)#define GPIO_PAR_CS_CS3_GPIO		(0x00)#define GPIO_PAR_CS_CS2_CS2		(0x04)#define GPIO_PAR_CS_CS2_GPIO		(0x00)#define GPIO_PAR_CS_CS1_CS1		(0x02)#define GPIO_PAR_CS_CS1_GPIO		(0x00)/* Bit definitions and macros for PAR_TIMER */#define GPIO_PAR_TIMER_T0IN(x)		(((x)&0x03))#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)#define GPIO_PAR_TIMER_T3IN_U2RXD	(0x40)#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)#define GPIO_PAR_TIMER_T2IN_U2TXD	(0x10)#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)#define GPIO_PAR_TIMER_T1IN_U2CTS	(0x04)#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)#define GPIO_PAR_TIMER_T0IN_U2RTS	(0x01)#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)/* Bit definitions and macros for PAR_USB */#define GPIO_PAR_USB_VBUSOC(x)		(((x)&0x03))#define GPIO_PAR_USB_VBUSEN(x)		(((x)&0x03)<<2)#define GPIO_PAR_USB_VBUSEN_MASK	(0xF3)#define GPIO_PAR_USB_VBUSEN_VBUSEN	(0x0C)#define GPIO_PAR_USB_VBUSEN_USBPULLUP	(0x08)#define GPIO_PAR_USB_VBUSEN_ULPI_NXT	(0x04)#define GPIO_PAR_USB_VBUSEN_GPIO	(0x00)#define GPIO_PAR_USB_VBUSOC_MASK	(0xFC)#define GPIO_PAR_USB_VBUSOC_VBUSOC	(0x03)#define GPIO_PAR_USB_VBUSOC_ULPI_STP	(0x01)#define GPIO_PAR_USB_VBUSOC_GPIO	(0x00)/* Bit definitions and macros for PAR_UART */
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