📄 m5445x.h

📁 U-boot源码 ARM7启动代码
💻 H
📖 第 1 页 / 共 5 页
字号:
#define INTC_IMRL_INT_MASK12		(0x00001000)#define INTC_IMRL_INT_MASK13		(0x00002000)#define INTC_IMRL_INT_MASK14		(0x00004000)#define INTC_IMRL_INT_MASK15		(0x00008000)#define INTC_IMRL_INT_MASK16		(0x00010000)#define INTC_IMRL_INT_MASK17		(0x00020000)#define INTC_IMRL_INT_MASK18		(0x00040000)#define INTC_IMRL_INT_MASK19		(0x00080000)#define INTC_IMRL_INT_MASK20		(0x00100000)#define INTC_IMRL_INT_MASK21		(0x00200000)#define INTC_IMRL_INT_MASK22		(0x00400000)#define INTC_IMRL_INT_MASK23		(0x00800000)#define INTC_IMRL_INT_MASK24		(0x01000000)#define INTC_IMRL_INT_MASK25		(0x02000000)#define INTC_IMRL_INT_MASK26		(0x04000000)#define INTC_IMRL_INT_MASK27		(0x08000000)#define INTC_IMRL_INT_MASK28		(0x10000000)#define INTC_IMRL_INT_MASK29		(0x20000000)#define INTC_IMRL_INT_MASK30		(0x40000000)#define INTC_IMRL_INT_MASK31		(0x80000000)/* Bit definitions and macros for INTFRCH */#define INTC_INTFRCH_INTFRC32		(0x00000001)#define INTC_INTFRCH_INTFRC33		(0x00000002)#define INTC_INTFRCH_INTFRC34		(0x00000004)#define INTC_INTFRCH_INTFRC35		(0x00000008)#define INTC_INTFRCH_INTFRC36		(0x00000010)#define INTC_INTFRCH_INTFRC37		(0x00000020)#define INTC_INTFRCH_INTFRC38		(0x00000040)#define INTC_INTFRCH_INTFRC39		(0x00000080)#define INTC_INTFRCH_INTFRC40		(0x00000100)#define INTC_INTFRCH_INTFRC41		(0x00000200)#define INTC_INTFRCH_INTFRC42		(0x00000400)#define INTC_INTFRCH_INTFRC43		(0x00000800)#define INTC_INTFRCH_INTFRC44		(0x00001000)#define INTC_INTFRCH_INTFRC45		(0x00002000)#define INTC_INTFRCH_INTFRC46		(0x00004000)#define INTC_INTFRCH_INTFRC47		(0x00008000)#define INTC_INTFRCH_INTFRC48		(0x00010000)#define INTC_INTFRCH_INTFRC49		(0x00020000)#define INTC_INTFRCH_INTFRC50		(0x00040000)#define INTC_INTFRCH_INTFRC51		(0x00080000)#define INTC_INTFRCH_INTFRC52		(0x00100000)#define INTC_INTFRCH_INTFRC53		(0x00200000)#define INTC_INTFRCH_INTFRC54		(0x00400000)#define INTC_INTFRCH_INTFRC55		(0x00800000)#define INTC_INTFRCH_INTFRC56		(0x01000000)#define INTC_INTFRCH_INTFRC57		(0x02000000)#define INTC_INTFRCH_INTFRC58		(0x04000000)#define INTC_INTFRCH_INTFRC59		(0x08000000)#define INTC_INTFRCH_INTFRC60		(0x10000000)#define INTC_INTFRCH_INTFRC61		(0x20000000)#define INTC_INTFRCH_INTFRC62		(0x40000000)#define INTC_INTFRCH_INTFRC63		(0x80000000)/* Bit definitions and macros for INTFRCL */#define INTC_INTFRCL_INTFRC0		(0x00000001)#define INTC_INTFRCL_INTFRC1		(0x00000002)#define INTC_INTFRCL_INTFRC2		(0x00000004)#define INTC_INTFRCL_INTFRC3		(0x00000008)#define INTC_INTFRCL_INTFRC4		(0x00000010)#define INTC_INTFRCL_INTFRC5		(0x00000020)#define INTC_INTFRCL_INTFRC6		(0x00000040)#define INTC_INTFRCL_INTFRC7		(0x00000080)#define INTC_INTFRCL_INTFRC8		(0x00000100)#define INTC_INTFRCL_INTFRC9		(0x00000200)#define INTC_INTFRCL_INTFRC10		(0x00000400)#define INTC_INTFRCL_INTFRC11		(0x00000800)#define INTC_INTFRCL_INTFRC12		(0x00001000)#define INTC_INTFRCL_INTFRC13		(0x00002000)#define INTC_INTFRCL_INTFRC14		(0x00004000)#define INTC_INTFRCL_INTFRC15		(0x00008000)#define INTC_INTFRCL_INTFRC16		(0x00010000)#define INTC_INTFRCL_INTFRC17		(0x00020000)#define INTC_INTFRCL_INTFRC18		(0x00040000)#define INTC_INTFRCL_INTFRC19		(0x00080000)#define INTC_INTFRCL_INTFRC20		(0x00100000)#define INTC_INTFRCL_INTFRC21		(0x00200000)#define INTC_INTFRCL_INTFRC22		(0x00400000)#define INTC_INTFRCL_INTFRC23		(0x00800000)#define INTC_INTFRCL_INTFRC24		(0x01000000)#define INTC_INTFRCL_INTFRC25		(0x02000000)#define INTC_INTFRCL_INTFRC26		(0x04000000)#define INTC_INTFRCL_INTFRC27		(0x08000000)#define INTC_INTFRCL_INTFRC28		(0x10000000)#define INTC_INTFRCL_INTFRC29		(0x20000000)#define INTC_INTFRCL_INTFRC30		(0x40000000)#define INTC_INTFRCL_INTFRC31		(0x80000000)/* Bit definitions and macros for ICONFIG */#define INTC_ICONFIG_EMASK		(0x0020)#define INTC_ICONFIG_ELVLPRI1		(0x0200)#define INTC_ICONFIG_ELVLPRI2		(0x0400)#define INTC_ICONFIG_ELVLPRI3		(0x0800)#define INTC_ICONFIG_ELVLPRI4		(0x1000)#define INTC_ICONFIG_ELVLPRI5		(0x2000)#define INTC_ICONFIG_ELVLPRI6		(0x4000)#define INTC_ICONFIG_ELVLPRI7		(0x8000)/* Bit definitions and macros for SIMR */#define INTC_SIMR_SIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CIMR */#define INTC_CIMR_CIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CLMASK */#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for SLMASK */#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for ICR group */#define INTC_ICR_IL(x)			(((x)&0x07))/********************************************************************** DMA Serial Peripheral Interface (DSPI)*********************************************************************//* Bit definitions and macros for DMCR */#define DSPI_DMCR_HALT			(0x00000001)#define DSPI_DMCR_SMPL_PT(x)		(((x)&0x00000003)<<8)#define DSPI_DMCR_CRXF			(0x00000400)#define DSPI_DMCR_CTXF			(0x00000800)#define DSPI_DMCR_DRXF			(0x00001000)#define DSPI_DMCR_DTXF			(0x00002000)#define DSPI_DMCR_CSIS0			(0x00010000)#define DSPI_DMCR_CSIS2			(0x00040000)#define DSPI_DMCR_CSIS3			(0x00080000)#define DSPI_DMCR_CSIS5			(0x00200000)#define DSPI_DMCR_ROOE			(0x01000000)#define DSPI_DMCR_PCSSE			(0x02000000)#define DSPI_DMCR_MTFE			(0x04000000)#define DSPI_DMCR_FRZ			(0x08000000)#define DSPI_DMCR_DCONF(x)		(((x)&0x00000003)<<28)#define DSPI_DMCR_CSCK			(0x40000000)#define DSPI_DMCR_MSTR			(0x80000000)/* Bit definitions and macros for DTCR */#define DSPI_DTCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)/* Bit definitions and macros for DCTAR group */#define DSPI_DCTAR_BR(x)		(((x)&0x0000000F))#define DSPI_DCTAR_DT(x)		(((x)&0x0000000F)<<4)#define DSPI_DCTAR_ASC(x)		(((x)&0x0000000F)<<8)#define DSPI_DCTAR_CSSCK(x)		(((x)&0x0000000F)<<12)#define DSPI_DCTAR_PBR(x)		(((x)&0x00000003)<<16)#define DSPI_DCTAR_PDT(x)		(((x)&0x00000003)<<18)#define DSPI_DCTAR_PASC(x)		(((x)&0x00000003)<<20)#define DSPI_DCTAR_PCSSCK(x)		(((x)&0x00000003)<<22)#define DSPI_DCTAR_LSBFE		(0x01000000)#define DSPI_DCTAR_CPHA			(0x02000000)#define DSPI_DCTAR_CPOL			(0x04000000)#define DSPI_DCTAR_TRSZ(x)		(((x)&0x0000000F)<<27)#define DSPI_DCTAR_PCSSCK_1CLK		(0x00000000)#define DSPI_DCTAR_PCSSCK_3CLK		(0x00400000)#define DSPI_DCTAR_PCSSCK_5CLK		(0x00800000)#define DSPI_DCTAR_PCSSCK_7CLK		(0x00A00000)#define DSPI_DCTAR_PASC_1CLK		(0x00000000)#define DSPI_DCTAR_PASC_3CLK		(0x00100000)#define DSPI_DCTAR_PASC_5CLK		(0x00200000)#define DSPI_DCTAR_PASC_7CLK		(0x00300000)#define DSPI_DCTAR_PDT_1CLK		(0x00000000)#define DSPI_DCTAR_PDT_3CLK		(0x00040000)#define DSPI_DCTAR_PDT_5CLK		(0x00080000)#define DSPI_DCTAR_PDT_7CLK		(0x000A0000)#define DSPI_DCTAR_PBR_1CLK		(0x00000000)#define DSPI_DCTAR_PBR_3CLK		(0x00010000)#define DSPI_DCTAR_PBR_5CLK		(0x00020000)#define DSPI_DCTAR_PBR_7CLK		(0x00030000)/* Bit definitions and macros for DSR */#define DSPI_DSR_RXPTR(x)		(((x)&0x0000000F))#define DSPI_DSR_RXCTR(x)		(((x)&0x0000000F)<<4)#define DSPI_DSR_TXPTR(x)		(((x)&0x0000000F)<<8)#define DSPI_DSR_TXCTR(x)		(((x)&0x0000000F)<<12)#define DSPI_DSR_RFDF			(0x00020000)#define DSPI_DSR_RFOF			(0x00080000)#define DSPI_DSR_TFFF			(0x02000000)#define DSPI_DSR_TFUF			(0x08000000)#define DSPI_DSR_EOQF			(0x10000000)#define DSPI_DSR_TXRXS			(0x40000000)#define DSPI_DSR_TCF			(0x80000000)/* Bit definitions and macros for DIRSR */#define DSPI_DIRSR_RFDFS		(0x00010000)#define DSPI_DIRSR_RFDFE		(0x00020000)#define DSPI_DIRSR_RFOFE		(0x00080000)#define DSPI_DIRSR_TFFFS		(0x01000000)#define DSPI_DIRSR_TFFFE		(0x02000000)#define DSPI_DIRSR_TFUFE		(0x08000000)#define DSPI_DIRSR_EOQFE		(0x10000000)#define DSPI_DIRSR_TCFE			(0x80000000)/* Bit definitions and macros for DTFR */#define DSPI_DTFR_TXDATA(x)		(((x)&0x0000FFFF))#define DSPI_DTFR_CS0			(0x00010000)#define DSPI_DTFR_CS2			(0x00040000)#define DSPI_DTFR_CS3			(0x00080000)#define DSPI_DTFR_CS5			(0x00200000)#define DSPI_DTFR_CTCNT			(0x04000000)#define DSPI_DTFR_EOQ			(0x08000000)#define DSPI_DTFR_CTAS(x)		(((x)&0x00000007)<<28)#define DSPI_DTFR_CONT			(0x80000000)/* Bit definitions and macros for DRFR */#define DSPI_DRFR_RXDATA(x)		(((x)&0x0000FFFF))/* Bit definitions and macros for DTFDR group */#define DSPI_DTFDR_TXDATA(x)		(((x)&0x0000FFFF))#define DSPI_DTFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)/* Bit definitions and macros for DRFDR group */#define DSPI_DRFDR_RXDATA(x)		(((x)&0x0000FFFF))/********************************************************************** Edge Port Module (EPORT)*********************************************************************//* Bit definitions and macros for EPPAR */#define EPORT_EPPAR_EPPA1(x)		(((x)&0x0003)<<2)#define EPORT_EPPAR_EPPA2(x)		(((x)&0x0003)<<4)#define EPORT_EPPAR_EPPA3(x)		(((x)&0x0003)<<6)#define EPORT_EPPAR_EPPA4(x)		(((x)&0x0003)<<8)#define EPORT_EPPAR_EPPA5(x)		(((x)&0x0003)<<10)#define EPORT_EPPAR_EPPA6(x)		(((x)&0x0003)<<12)#define EPORT_EPPAR_EPPA7(x)		(((x)&0x0003)<<14)#define EPORT_EPPAR_LEVEL		(0)#define EPORT_EPPAR_RISING		(1)#define EPORT_EPPAR_FALLING		(2)#define EPORT_EPPAR_BOTH		(3)#define EPORT_EPPAR_EPPA7_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA7_RISING	(0x4000)#define EPORT_EPPAR_EPPA7_FALLING	(0x8000)#define EPORT_EPPAR_EPPA7_BOTH		(0xC000)#define EPORT_EPPAR_EPPA6_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA6_RISING	(0x1000)#define EPORT_EPPAR_EPPA6_FALLING	(0x2000)#define EPORT_EPPAR_EPPA6_BOTH		(0x3000)#define EPORT_EPPAR_EPPA5_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA5_RISING	(0x0400)#define EPORT_EPPAR_EPPA5_FALLING	(0x0800)#define EPORT_EPPAR_EPPA5_BOTH		(0x0C00)#define EPORT_EPPAR_EPPA4_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA4_RISING	(0x0100)#define EPORT_EPPAR_EPPA4_FALLING	(0x0200)#define EPORT_EPPAR_EPPA4_BOTH		(0x0300)#define EPORT_EPPAR_EPPA3_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA3_RISING	(0x0040)#define EPORT_EPPAR_EPPA3_FALLING	(0x0080)#define EPORT_EPPAR_EPPA3_BOTH		(0x00C0)#define EPORT_EPPAR_EPPA2_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA2_RISING	(0x0010)#define EPORT_EPPAR_EPPA2_FALLING	(0x0020)#define EPORT_EPPAR_EPPA2_BOTH		(0x0030)#define EPORT_EPPAR_EPPA1_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA1_RISING	(0x0004)#define EPORT_EPPAR_EPPA1_FALLING	(0x0008)#define EPORT_EPPAR_EPPA1_BOTH		(0x000C)/* Bit definitions and macros for EPDDR */#define EPORT_EPDDR_EPDD1		(0x02)#define EPORT_EPDDR_EPDD2		(0x04)#define EPORT_EPDDR_EPDD3		(0x08)#define EPORT_EPDDR_EPDD4		(0x10)#define EPORT_EPDDR_EPDD5		(0x20)#define EPORT_EPDDR_EPDD6		(0x40)#define EPORT_EPDDR_EPDD7		(0x80)/* Bit definitions and macros for EPIER */#define EPORT_EPIER_EPIE1		(0x02)#define EPORT_EPIER_EPIE2		(0x04)#define EPORT_EPIER_EPIE3		(0x08)#define EPORT_EPIER_EPIE4		(0x10)#define EPORT_EPIER_EPIE5		(0x20)#define EPORT_EPIER_EPIE6		(0x40)#define EPORT_EPIER_EPIE7		(0x80)/* Bit definitions and macros for EPDR */#define EPORT_EPDR_EPD1			(0x02)#define EPORT_EPDR_EPD2			(0x04)#define EPORT_EPDR_EPD3			(0x08)#define EPORT_EPDR_EPD4			(0x10)#define EPORT_EPDR_EPD5			(0x20)#define EPORT_EPDR_EPD6			(0x40)#define EPORT_EPDR_EPD7			(0x80)/* Bit definitions and macros for EPPDR */#define EPORT_EPPDR_EPPD1		(0x02)#define EPORT_EPPDR_EPPD2		(0x04)#define EPORT_EPPDR_EPPD3		(0x08)#define EPORT_EPPDR_EPPD4		(0x10)#define EPORT_EPPDR_EPPD5		(0x20)#define EPORT_EPPDR_EPPD6		(0x40)#define EPORT_EPPDR_EPPD7		(0x80)/* Bit definitions and macros for EPFR */#define EPORT_EPFR_EPF1			(0x02)#define EPORT_EPFR_EPF2			(0x04)#define EPORT_EPFR_EPF3			(0x08)#define EPORT_EPFR_EPF4			(0x10)#define EPORT_EPFR_EPF5			(0x20)#define EPORT_EPFR_EPF6			(0x40)#define EPORT_EPFR_EPF7			(0x80)/********************************************************************** Watchdog Timer Modules (WTM)*********************************************************************//* Bit definitions and macros for WCR */
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -