📄 m5445x.h

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/* * MCF5445x Internal Memory Map * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __MCF5445X__#define __MCF5445X__/********************************************************************** Cross-bar switch (XBS)*********************************************************************//* Bit definitions and macros for PRS group */#define XBS_PRS_M0(x)			(((x)&0x00000007))	/* Core */#define XBS_PRS_M1(x)			(((x)&0x00000007)<<4)	/* eDMA */#define XBS_PRS_M2(x)			(((x)&0x00000007)<<8)	/* FEC0 */#define XBS_PRS_M3(x)			(((x)&0x00000007)<<12)	/* FEC1 */#define XBS_PRS_M5(x)			(((x)&0x00000007)<<20)	/* PCI controller */#define XBS_PRS_M6(x)			(((x)&0x00000007)<<24)	/* USB OTG */#define XBS_PRS_M7(x)			(((x)&0x00000007)<<28)	/* Serial Boot *//* Bit definitions and macros for CRS group */#define XBS_CRS_PARK(x)			(((x)&0x00000007))	/* Master parking ctrl */#define XBS_CRS_PCTL(x)			(((x)&0x00000003)<<4)	/* Parking mode ctrl */#define XBS_CRS_ARB			(0x00000100)	/* Arbitration Mode */#define XBS_CRS_RO			(0x80000000)	/* Read Only */#define XBS_CRS_PCTL_PARK_FIELD		(0)#define XBS_CRS_PCTL_PARK_ON_LAST	(1)#define XBS_CRS_PCTL_PARK_NONE		(2)#define XBS_CRS_PCTL_PARK_CORE		(0)#define XBS_CRS_PCTL_PARK_EDMA		(1)#define XBS_CRS_PCTL_PARK_FEC0		(2)#define XBS_CRS_PCTL_PARK_FEC1		(3)#define XBS_CRS_PCTL_PARK_PCI		(5)#define XBS_CRS_PCTL_PARK_USB		(6)#define XBS_CRS_PCTL_PARK_SBF		(7)/********************************************************************** FlexBus Chip Selects (FBCS)*********************************************************************//* Bit definitions and macros for CSAR group */#define FBCS_CSAR_BA(x)			((x)&0xFFFF0000)/* Bit definitions and macros for CSMR group */#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */#define FBCS_CSMR_WP			(0x00000100)	/* Write protect */#define FBCS_CSMR_BAM(x)		(((x)&0x0000FFFF)<<16)	/* Base address mask */#define FBCS_CSMR_BAM_4G		(0xFFFF0000)#define FBCS_CSMR_BAM_2G		(0x7FFF0000)#define FBCS_CSMR_BAM_1G		(0x3FFF0000)#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)#define FBCS_CSMR_BAM_512M		(0x1FFF0000)#define FBCS_CSMR_BAM_256M		(0x0FFF0000)#define FBCS_CSMR_BAM_128M		(0x07FF0000)#define FBCS_CSMR_BAM_64M		(0x03FF0000)#define FBCS_CSMR_BAM_32M		(0x01FF0000)#define FBCS_CSMR_BAM_16M		(0x00FF0000)#define FBCS_CSMR_BAM_8M		(0x007F0000)#define FBCS_CSMR_BAM_4M		(0x003F0000)#define FBCS_CSMR_BAM_2M		(0x001F0000)#define FBCS_CSMR_BAM_1M		(0x000F0000)#define FBCS_CSMR_BAM_1024K		(0x000F0000)#define FBCS_CSMR_BAM_512K		(0x00070000)#define FBCS_CSMR_BAM_256K		(0x00030000)#define FBCS_CSMR_BAM_128K		(0x00010000)#define FBCS_CSMR_BAM_64K		(0x00000000)/* Bit definitions and macros for CSCR group */#define FBCS_CSCR_BSTW			(0x00000008)	/* Burst-write enable */#define FBCS_CSCR_BSTR			(0x00000010)	/* Burst-read enable */#define FBCS_CSCR_BEM			(0x00000020)	/* Byte-enable mode */#define FBCS_CSCR_PS(x)			(((x)&0x00000003)<<6)	/* Port size */#define FBCS_CSCR_AA			(0x00000100)	/* Auto-acknowledge */#define FBCS_CSCR_WS(x)			(((x)&0x0000003F)<<10)	/* Wait states */#define FBCS_CSCR_WRAH(x)		(((x)&0x00000003)<<16)	/* Write address hold or deselect */#define FBCS_CSCR_RDAH(x)		(((x)&0x00000003)<<18)	/* Read address hold or deselect */#define FBCS_CSCR_ASET(x)		(((x)&0x00000003)<<20)	/* Address setup */#define FBCS_CSCR_SWSEN			(0x00800000)	/* Secondary wait state enable */#define FBCS_CSCR_SWS(x)		(((x)&0x0000003F)<<26)	/* Secondary wait states */#define FBCS_CSCR_PS_8			(0x00000040)#define FBCS_CSCR_PS_16			(0x00000080)#define FBCS_CSCR_PS_32			(0x00000000)/********************************************************************** Interrupt Controller (INTC)*********************************************************************/#define INT0_LO_RSVD0			(0)#define INT0_LO_EPORT1			(1)#define INT0_LO_EPORT2			(2)#define INT0_LO_EPORT3			(3)#define INT0_LO_EPORT4			(4)#define INT0_LO_EPORT5			(5)#define INT0_LO_EPORT6			(6)#define INT0_LO_EPORT7			(7)#define INT0_LO_EDMA_00			(8)#define INT0_LO_EDMA_01			(9)#define INT0_LO_EDMA_02			(10)#define INT0_LO_EDMA_03			(11)#define INT0_LO_EDMA_04			(12)#define INT0_LO_EDMA_05			(13)#define INT0_LO_EDMA_06			(14)#define INT0_LO_EDMA_07			(15)#define INT0_LO_EDMA_08			(16)#define INT0_LO_EDMA_09			(17)#define INT0_LO_EDMA_10			(18)#define INT0_LO_EDMA_11			(19)#define INT0_LO_EDMA_12			(20)#define INT0_LO_EDMA_13			(21)#define INT0_LO_EDMA_14			(22)#define INT0_LO_EDMA_15			(23)#define INT0_LO_EDMA_ERR		(24)#define INT0_LO_SCM			(25)#define INT0_LO_UART0			(26)#define INT0_LO_UART1			(27)#define INT0_LO_UART2			(28)#define INT0_LO_RSVD1			(29)#define INT0_LO_I2C			(30)#define INT0_LO_QSPI			(31)#define INT0_HI_DTMR0			(32)#define INT0_HI_DTMR1			(33)#define INT0_HI_DTMR2			(34)#define INT0_HI_DTMR3			(35)#define INT0_HI_FEC0_TXF		(36)#define INT0_HI_FEC0_TXB		(37)#define INT0_HI_FEC0_UN			(38)#define INT0_HI_FEC0_RL			(39)#define INT0_HI_FEC0_RXF		(40)#define INT0_HI_FEC0_RXB		(41)#define INT0_HI_FEC0_MII		(42)#define INT0_HI_FEC0_LC			(43)#define INT0_HI_FEC0_HBERR		(44)#define INT0_HI_FEC0_GRA		(45)#define INT0_HI_FEC0_EBERR		(46)#define INT0_HI_FEC0_BABT		(47)#define INT0_HI_FEC0_BABR		(48)#define INT0_HI_FEC1_TXF		(49)#define INT0_HI_FEC1_TXB		(50)#define INT0_HI_FEC1_UN			(51)#define INT0_HI_FEC1_RL			(52)#define INT0_HI_FEC1_RXF		(53)#define INT0_HI_FEC1_RXB		(54)#define INT0_HI_FEC1_MII		(55)#define INT0_HI_FEC1_LC			(56)#define INT0_HI_FEC1_HBERR		(57)#define INT0_HI_FEC1_GRA		(58)#define INT0_HI_FEC1_EBERR		(59)#define INT0_HI_FEC1_BABT		(60)#define INT0_HI_FEC1_BABR		(61)#define INT0_HI_SCMIR			(62)#define INT0_HI_RTC_ISR			(63)#define INT1_HI_DSPI_EOQF		(33)#define INT1_HI_DSPI_TFFF		(34)#define INT1_HI_DSPI_TCF		(35)#define INT1_HI_DSPI_TFUF		(36)#define INT1_HI_DSPI_RFDF		(37)#define INT1_HI_DSPI_RFOF		(38)#define INT1_HI_DSPI_RFOF_TFUF		(39)#define INT1_HI_RNG_EI			(40)#define INT1_HI_PIT0_PIF		(43)#define INT1_HI_PIT1_PIF		(44)#define INT1_HI_PIT2_PIF		(45)#define INT1_HI_PIT3_PIF		(46)#define INT1_HI_USBOTG_USBSTS		(47)#define INT1_HI_SSI_ISR			(49)#define INT1_HI_CCM_UOCSR		(53)#define INT1_HI_ATA_ISR			(54)#define INT1_HI_PCI_SCR			(55)#define INT1_HI_PCI_ASR			(56)#define INT1_HI_PLL_LOCKS		(57)/* Bit definitions and macros for IPRH */#define INTC_IPRH_INT32			(0x00000001)#define INTC_IPRH_INT33			(0x00000002)#define INTC_IPRH_INT34			(0x00000004)#define INTC_IPRH_INT35			(0x00000008)#define INTC_IPRH_INT36			(0x00000010)#define INTC_IPRH_INT37			(0x00000020)#define INTC_IPRH_INT38			(0x00000040)#define INTC_IPRH_INT39			(0x00000080)#define INTC_IPRH_INT40			(0x00000100)#define INTC_IPRH_INT41			(0x00000200)#define INTC_IPRH_INT42			(0x00000400)#define INTC_IPRH_INT43			(0x00000800)#define INTC_IPRH_INT44			(0x00001000)#define INTC_IPRH_INT45			(0x00002000)#define INTC_IPRH_INT46			(0x00004000)#define INTC_IPRH_INT47			(0x00008000)#define INTC_IPRH_INT48			(0x00010000)#define INTC_IPRH_INT49			(0x00020000)#define INTC_IPRH_INT50			(0x00040000)#define INTC_IPRH_INT51			(0x00080000)#define INTC_IPRH_INT52			(0x00100000)#define INTC_IPRH_INT53			(0x00200000)#define INTC_IPRH_INT54			(0x00400000)#define INTC_IPRH_INT55			(0x00800000)#define INTC_IPRH_INT56			(0x01000000)#define INTC_IPRH_INT57			(0x02000000)#define INTC_IPRH_INT58			(0x04000000)#define INTC_IPRH_INT59			(0x08000000)#define INTC_IPRH_INT60			(0x10000000)#define INTC_IPRH_INT61			(0x20000000)#define INTC_IPRH_INT62			(0x40000000)#define INTC_IPRH_INT63			(0x80000000)/* Bit definitions and macros for IPRL */#define INTC_IPRL_INT0			(0x00000001)#define INTC_IPRL_INT1			(0x00000002)#define INTC_IPRL_INT2			(0x00000004)#define INTC_IPRL_INT3			(0x00000008)#define INTC_IPRL_INT4			(0x00000010)#define INTC_IPRL_INT5			(0x00000020)#define INTC_IPRL_INT6			(0x00000040)#define INTC_IPRL_INT7			(0x00000080)#define INTC_IPRL_INT8			(0x00000100)#define INTC_IPRL_INT9			(0x00000200)#define INTC_IPRL_INT10			(0x00000400)#define INTC_IPRL_INT11			(0x00000800)#define INTC_IPRL_INT12			(0x00001000)#define INTC_IPRL_INT13			(0x00002000)#define INTC_IPRL_INT14			(0x00004000)#define INTC_IPRL_INT15			(0x00008000)#define INTC_IPRL_INT16			(0x00010000)#define INTC_IPRL_INT17			(0x00020000)#define INTC_IPRL_INT18			(0x00040000)#define INTC_IPRL_INT19			(0x00080000)#define INTC_IPRL_INT20			(0x00100000)#define INTC_IPRL_INT21			(0x00200000)#define INTC_IPRL_INT22			(0x00400000)#define INTC_IPRL_INT23			(0x00800000)#define INTC_IPRL_INT24			(0x01000000)#define INTC_IPRL_INT25			(0x02000000)#define INTC_IPRL_INT26			(0x04000000)#define INTC_IPRL_INT27			(0x08000000)#define INTC_IPRL_INT28			(0x10000000)#define INTC_IPRL_INT29			(0x20000000)#define INTC_IPRL_INT30			(0x40000000)#define INTC_IPRL_INT31			(0x80000000)/* Bit definitions and macros for IMRH */#define INTC_IMRH_INT_MASK32		(0x00000001)#define INTC_IMRH_INT_MASK33		(0x00000002)#define INTC_IMRH_INT_MASK34		(0x00000004)#define INTC_IMRH_INT_MASK35		(0x00000008)#define INTC_IMRH_INT_MASK36		(0x00000010)#define INTC_IMRH_INT_MASK37		(0x00000020)#define INTC_IMRH_INT_MASK38		(0x00000040)#define INTC_IMRH_INT_MASK39		(0x00000080)#define INTC_IMRH_INT_MASK40		(0x00000100)#define INTC_IMRH_INT_MASK41		(0x00000200)#define INTC_IMRH_INT_MASK42		(0x00000400)#define INTC_IMRH_INT_MASK43		(0x00000800)#define INTC_IMRH_INT_MASK44		(0x00001000)#define INTC_IMRH_INT_MASK45		(0x00002000)#define INTC_IMRH_INT_MASK46		(0x00004000)#define INTC_IMRH_INT_MASK47		(0x00008000)#define INTC_IMRH_INT_MASK48		(0x00010000)#define INTC_IMRH_INT_MASK49		(0x00020000)#define INTC_IMRH_INT_MASK50		(0x00040000)#define INTC_IMRH_INT_MASK51		(0x00080000)#define INTC_IMRH_INT_MASK52		(0x00100000)#define INTC_IMRH_INT_MASK53		(0x00200000)#define INTC_IMRH_INT_MASK54		(0x00400000)#define INTC_IMRH_INT_MASK55		(0x00800000)#define INTC_IMRH_INT_MASK56		(0x01000000)#define INTC_IMRH_INT_MASK57		(0x02000000)#define INTC_IMRH_INT_MASK58		(0x04000000)#define INTC_IMRH_INT_MASK59		(0x08000000)#define INTC_IMRH_INT_MASK60		(0x10000000)#define INTC_IMRH_INT_MASK61		(0x20000000)#define INTC_IMRH_INT_MASK62		(0x40000000)#define INTC_IMRH_INT_MASK63		(0x80000000)/* Bit definitions and macros for IMRL */#define INTC_IMRL_INT_MASK0		(0x00000001)#define INTC_IMRL_INT_MASK1		(0x00000002)#define INTC_IMRL_INT_MASK2		(0x00000004)#define INTC_IMRL_INT_MASK3		(0x00000008)#define INTC_IMRL_INT_MASK4		(0x00000010)#define INTC_IMRL_INT_MASK5		(0x00000020)#define INTC_IMRL_INT_MASK6		(0x00000040)#define INTC_IMRL_INT_MASK7		(0x00000080)#define INTC_IMRL_INT_MASK8		(0x00000100)#define INTC_IMRL_INT_MASK9		(0x00000200)#define INTC_IMRL_INT_MASK10		(0x00000400)#define INTC_IMRL_INT_MASK11		(0x00000800)
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