immap_5445x.h

U-boot源码 ARM7启动代码

/*
 * MCF5445x Internal Memory Map
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([e-mail])
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__

/* Module Base Addresses */
#define MMAP_SCM1	0xFC000000
#define MMAP_XBS	0xFC004000
#define MMAP_FBCS	0xFC008000
#define MMAP_FEC0	0xFC030000
#define MMAP_FEC1	0xFC034000
#define MMAP_RTC	0xFC03C000
#define MMAP_EDMA	0xFC044000
#define MMAP_INTC0	0xFC048000
#define MMAP_INTC1	0xFC04C000
#define MMAP_IACK	0xFC054000
#define MMAP_I2C	0xFC058000
#define MMAP_DSPI	0xFC05C000
#define MMAP_UART0	0xFC060000
#define MMAP_UART1	0xFC064000
#define MMAP_UART2	0xFC068000
#define MMAP_DTMR0	0xFC070000
#define MMAP_DTMR1	0xFC074000
#define MMAP_DTMR2	0xFC078000
#define MMAP_DTMR3	0xFC07C000
#define MMAP_PIT0	0xFC080000
#define MMAP_PIT1	0xFC084000
#define MMAP_PIT2	0xFC088000
#define MMAP_PIT3	0xFC08C000
#define MMAP_EPORT	0xFC094000
#define MMAP_WTM	0xFC098000
#define MMAP_SBF	0xFC0A0000
#define MMAP_RCM	0xFC0A0000
#define MMAP_CCM	0xFC0A0000
#define MMAP_GPIO	0xFC0A4000
#define MMAP_PCI	0xFC0A8000
#define MMAP_PCIARB	0xFC0AC000
#define MMAP_RNG	0xFC0B4000
#define MMAP_SDRAM	0xFC0B8000
#define MMAP_SSI	0xFC0BC000
#define MMAP_PLL	0xFC0C4000
#define MMAP_ATA	0x90000000

/*********************************************************************
* ATA
*********************************************************************/

typedef struct atac {
	/* PIO */
	u8 toff;		/* 0x00 */
	u8 ton;			/* 0x01 */
	u8 t1;			/* 0x02 */
	u8 t2w;			/* 0x03 */
	u8 t2r;			/* 0x04 */
	u8 ta;			/* 0x05 */
	u8 trd;			/* 0x06 */
	u8 t4;			/* 0x07 */
	u8 t9;			/* 0x08 */

	/* DMA */
	u8 tm;			/* 0x09 */
	u8 tn;			/* 0x0A */
	u8 td;			/* 0x0B */
	u8 tk;			/* 0x0C */
	u8 tack;		/* 0x0D */
	u8 tenv;		/* 0x0E */
	u8 trp;			/* 0x0F */
	u8 tzah;		/* 0x10 */
	u8 tmli;		/* 0x11 */
	u8 tdvh;		/* 0x12 */
	u8 tdzfs;		/* 0x13 */
	u8 tdvs;		/* 0x14 */
	u8 tcvh;		/* 0x15 */
	u8 tss;			/* 0x16 */
	u8 tcyc;		/* 0x17 */

	/* FIFO */
	u32 fifo32;		/* 0x18 */
	u16 fifo16;		/* 0x1C */
	u8 rsvd0[2];
	u8 ffill;		/* 0x20 */
	u8 rsvd1[3];

	/* ATA */
	u8 cr;			/* 0x24 */
	u8 rsvd2[3];
	u8 isr;			/* 0x28 */
	u8 rsvd3[3];
	u8 ier;			/* 0x2C */
	u8 rsvd4[3];
	u8 icr;			/* 0x30 */
	u8 rsvd5[3];
	u8 falarm;		/* 0x34 */
	u8 rsvd6[106];
} atac_t;

/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/

typedef struct xbs {
	u8 resv0[0x100];
	u32 prs1;		/* XBS Priority Register */
	u8 resv1[0xC];
	u32 crs1;		/* XBS Control Register */
	u8 resv2[0xEC];
	u32 prs2;		/* XBS Priority Register */
	u8 resv3[0xC];
	u32 crs2;		/* XBS Control Register */
	u8 resv4[0xEC];
	u32 prs3;		/* XBS Priority Register */
	u8 resv5[0xC];
	u32 crs3;		/* XBS Control Register */
	u8 resv6[0xEC];
	u32 prs4;		/* XBS Priority Register */
	u8 resv7[0xC];
	u32 crs4;		/* XBS Control Register */
	u8 resv8[0xEC];
	u32 prs5;		/* XBS Priority Register */
	u8 resv9[0xC];
	u32 crs5;		/* XBS Control Register */
	u8 resv10[0xEC];
	u32 prs6;		/* XBS Priority Register */
	u8 resv11[0xC];
	u32 crs6;		/* XBS Control Register */
	u8 resv12[0xEC];
	u32 prs7;		/* XBS Priority Register */
	u8 resv13[0xC];
	u32 crs7;		/* XBS Control Register */
} xbs_t;

/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/

typedef struct fbcs {
	u32 csar0;		/* Chip-select Address Register */
	u32 csmr0;		/* Chip-select Mask Register */
	u32 cscr0;		/* Chip-select Control Register */
	u32 csar1;		/* Chip-select Address Register */
	u32 csmr1;		/* Chip-select Mask Register */
	u32 cscr1;		/* Chip-select Control Register */
	u32 csar2;		/* Chip-select Address Register */
	u32 csmr2;		/* Chip-select Mask Register */
	u32 cscr2;		/* Chip-select Control Register */
	u32 csar3;		/* Chip-select Address Register */
	u32 csmr3;		/* Chip-select Mask Register */
	u32 cscr3;		/* Chip-select Control Register */
} fbcs_t;

/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/

typedef struct edma {
	u32 cr;
	u32 es;
	u8 resv0[0x6];
	u16 erq;
	u8 resv1[0x6];
	u16 eei;
	u8 serq;
	u8 cerq;
	u8 seei;
	u8 ceei;
	u8 cint;
	u8 cerr;
	u8 ssrt;
	u8 cdne;
	u8 resv2[0x6];
	u16 intr;
	u8 resv3[0x6];
	u16 err;
	u8 resv4[0xD0];
	u8 dchpri0;
	u8 dchpri1;
	u8 dchpri2;
	u8 dchpri3;
	u8 dchpri4;
	u8 dchpri5;
	u8 dchpri6;
	u8 dchpri7;
	u8 dchpri8;
	u8 dchpri9;
	u8 dchpri10;
	u8 dchpri11;
	u8 dchpri12;
	u8 dchpri13;
	u8 dchpri14;
	u8 dchpri15;
	u8 resv5[0xEF0];
	u32 tcd0_saddr;
	u16 tcd0_attr;
	u16 tcd0_soff;
	u32 tcd0_nbytes;
	u32 tcd0_slast;
	u32 tcd0_daddr;
	union {
		u16 tcd0_citer_elink;
		u16 tcd0_citer;
	};
	u16 tcd0_doff;
	u32 tcd0_dlast_sga;
	union {
		u16 tcd0_biter_elink;
		u16 tcd0_biter;
	};
	u16 tcd0_csr;
	u32 tcd1_saddr;
	u16 tcd1_attr;
	u16 tcd1_soff;
	u32 tcd1_nbytes;
	u32 tcd1_slast;
	u32 tcd1_daddr;
	union {
		u16 tcd1_citer_elink;
		u16 tcd1_citer;
	};
	u16 tcd1_doff;
	u32 tcd1_dlast_sga;
	union {
		u16 tcd1_biter;
		u16 tcd1_biter_elink;
	};
	u16 tcd1_csr;
	u32 tcd2_saddr;
	u16 tcd2_attr;
	u16 tcd2_soff;
	u32 tcd2_nbytes;
	u32 tcd2_slast;
	u32 tcd2_daddr;
	union {
		u16 tcd2_citer;
		u16 tcd2_citer_elink;
	};
	u16 tcd2_doff;
	u32 tcd2_dlast_sga;
	union {
		u16 tcd2_biter_elink;
		u16 tcd2_biter;
	};
	u16 tcd2_csr;
	u32 tcd3_saddr;
	u16 tcd3_attr;
	u16 tcd3_soff;
	u32 tcd3_nbytes;
	u32 tcd3_slast;
	u32 tcd3_daddr;
	union {
		u16 tcd3_citer;
		u16 tcd3_citer_elink;
	};
	u16 tcd3_doff;
	u32 tcd3_dlast_sga;
	union {
		u16 tcd3_biter_elink;
		u16 tcd3_biter;
	};
	u16 tcd3_csr;
	u32 tcd4_saddr;
	u16 tcd4_attr;
	u16 tcd4_soff;
	u32 tcd4_nbytes;
	u32 tcd4_slast;
	u32 tcd4_daddr;
	union {
		u16 tcd4_citer;
		u16 tcd4_citer_elink;
	};
	u16 tcd4_doff;
	u32 tcd4_dlast_sga;
	union {
		u16 tcd4_biter;
		u16 tcd4_biter_elink;
	};
	u16 tcd4_csr;
	u32 tcd5_saddr;
	u16 tcd5_attr;
	u16 tcd5_soff;
	u32 tcd5_nbytes;
	u32 tcd5_slast;
	u32 tcd5_daddr;
	union {
		u16 tcd5_citer;
		u16 tcd5_citer_elink;
	};
	u16 tcd5_doff;
	u32 tcd5_dlast_sga;
	union {
		u16 tcd5_biter_elink;
		u16 tcd5_biter;
	};
	u16 tcd5_csr;
	u32 tcd6_saddr;
	u16 tcd6_attr;
	u16 tcd6_soff;
	u32 tcd6_nbytes;
	u32 tcd6_slast;
	u32 tcd6_daddr;
	union {
		u16 tcd6_citer;
		u16 tcd6_citer_elink;
	};
	u16 tcd6_doff;
	u32 tcd6_dlast_sga;
	union {
		u16 tcd6_biter_elink;
		u16 tcd6_biter;
	};
	u16 tcd6_csr;
	u32 tcd7_saddr;
	u16 tcd7_attr;
	u16 tcd7_soff;
	u32 tcd7_nbytes;
	u32 tcd7_slast;
	u32 tcd7_daddr;
	union {
		u16 tcd7_citer;
		u16 tcd7_citer_elink;
	};
	u16 tcd7_doff;
	u32 tcd7_dlast_sga;
	union {
		u16 tcd7_biter_elink;
		u16 tcd7_biter;
	};
	u16 tcd7_csr;
	u32 tcd8_saddr;
	u16 tcd8_attr;
	u16 tcd8_soff;
	u32 tcd8_nbytes;
	u32 tcd8_slast;
	u32 tcd8_daddr;
	union {
		u16 tcd8_citer;
		u16 tcd8_citer_elink;
	};
	u16 tcd8_doff;
	u32 tcd8_dlast_sga;
	union {
		u16 tcd8_biter_elink;
		u16 tcd8_biter;
	};
	u16 tcd8_csr;
	u32 tcd9_saddr;
	u16 tcd9_attr;
	u16 tcd9_soff;
	u32 tcd9_nbytes;
	u32 tcd9_slast;
	u32 tcd9_daddr;
	union {
		u16 tcd9_citer_elink;
		u16 tcd9_citer;
	};
	u16 tcd9_doff;
	u32 tcd9_dlast_sga;
	union {
		u16 tcd9_biter_elink;
		u16 tcd9_biter;
	};
	u16 tcd9_csr;
	u32 tcd10_saddr;
	u16 tcd10_attr;
	u16 tcd10_soff;
	u32 tcd10_nbytes;
	u32 tcd10_slast;
	u32 tcd10_daddr;
	union {
		u16 tcd10_citer_elink;
		u16 tcd10_citer;
	};
	u16 tcd10_doff;
	u32 tcd10_dlast_sga;
	union {
		u16 tcd10_biter;
		u16 tcd10_biter_elink;
	};
	u16 tcd10_csr;
	u32 tcd11_saddr;
	u16 tcd11_attr;
	u16 tcd11_soff;
	u32 tcd11_nbytes;
	u32 tcd11_slast;
	u32 tcd11_daddr;
	union {
		u16 tcd11_citer;
		u16 tcd11_citer_elink;
	};
	u16 tcd11_doff;
	u32 tcd11_dlast_sga;
	union {
		u16 tcd11_biter;
		u16 tcd11_biter_elink;
	};
	u16 tcd11_csr;
	u32 tcd12_saddr;
	u16 tcd12_attr;
	u16 tcd12_soff;
	u32 tcd12_nbytes;
	u32 tcd12_slast;
	u32 tcd12_daddr;
	union {
		u16 tcd12_citer;
		u16 tcd12_citer_elink;
	};
	u16 tcd12_doff;
	u32 tcd12_dlast_sga;
	union {
		u16 tcd12_biter;
		u16 tcd12_biter_elink;
	};
	u16 tcd12_csr;
	u32 tcd13_saddr;
	u16 tcd13_attr;
	u16 tcd13_soff;
	u32 tcd13_nbytes;
	u32 tcd13_slast;
	u32 tcd13_daddr;
	union {
		u16 tcd13_citer_elink;
		u16 tcd13_citer;
	};
	u16 tcd13_doff;
	u32 tcd13_dlast_sga;
	union {
		u16 tcd13_biter_elink;
		u16 tcd13_biter;
	};
	u16 tcd13_csr;
	u32 tcd14_saddr;
	u16 tcd14_attr;
	u16 tcd14_soff;
	u32 tcd14_nbytes;
	u32 tcd14_slast;
	u32 tcd14_daddr;
	union {
		u16 tcd14_citer;
		u16 tcd14_citer_elink;
	};
	u16 tcd14_doff;
	u32 tcd14_dlast_sga;
	union {
		u16 tcd14_biter_elink;
		u16 tcd14_biter;
	};
	u16 tcd14_csr;