radeon.h

U-boot源码 ARM7启动代码

#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT		0x00008000L
#define CLK_PWRMGT_CNTL__MC_BUSY_MASK			0x00010000L
#define CLK_PWRMGT_CNTL__MC_BUSY			0x00010000L
#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK		0x00020000L
#define CLK_PWRMGT_CNTL__MC_INT_CNTL			0x00020000L
#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK			0x00040000L
#define CLK_PWRMGT_CNTL__MC_SWITCH			0x00040000L
#define CLK_PWRMGT_CNTL__DLL_READY_MASK			0x00080000L
#define CLK_PWRMGT_CNTL__DLL_READY			0x00080000L
#define CLK_PWRMGT_CNTL__DISP_PM_MASK			0x00100000L
#define CLK_PWRMGT_CNTL__DISP_PM			0x00100000L
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK		0x00e00000L
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK		0x3f000000L
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK		0x40000000L
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF		0x40000000L
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK		0x80000000L
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF			0x80000000L

/* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE_MASK			0x00000001L
#define BUS_CNTL1__PMI_IO_DISABLE			0x00000001L
#define BUS_CNTL1__PMI_MEM_DISABLE_MASK			0x00000002L
#define BUS_CNTL1__PMI_MEM_DISABLE			0x00000002L
#define BUS_CNTL1__PMI_BM_DISABLE_MASK			0x00000004L
#define BUS_CNTL1__PMI_BM_DISABLE			0x00000004L
#define BUS_CNTL1__PMI_INT_DISABLE_MASK			0x00000008L
#define BUS_CNTL1__PMI_INT_DISABLE			0x00000008L
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK	0x00000020L
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE		0x00000020L
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK	0x00000100L
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS		0x00000100L
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK	0x00000200L
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS		0x00000200L
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK	0x00000400L
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS		0x00000400L
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS	0x00000800L
#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK		0x0c000000L
#define BUS_CNTL1__SEND_SBA_LATENCY_MASK		0x70000000L
#define BUS_CNTL1__AGPCLK_VALID_MASK			0x80000000L
#define BUS_CNTL1__AGPCLK_VALID				0x80000000L

/* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT		0x00000000
#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT		0x00000001
#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT		0x00000002
#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT		0x00000003
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT	0x00000005
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT	0x00000008
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT	0x00000009
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT	0x0000000a
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT		0x0000001a
#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT		0x0000001c
#define BUS_CNTL1__AGPCLK_VALID__SHIFT			0x0000001f

/* CRTC_OFFSET_CNTL */
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK		0x0000000fL
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK	0x000000f0L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK	0x00004000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT		0x00004000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK		0x00008000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN			0x00008000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK	0x00010000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL		0x00010000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK	0x00020000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN		0x00020000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK	0x000c0000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK	0x00100000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN	0x00100000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK		0x00200000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC		0x00200000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN	0x10000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN	0x20000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK	0x40000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET		0x40000000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK		0x80000000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK		0x80000000L

/* CRTC_GEN_CNTL */
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK		0x00000001L
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN			0x00000001L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK		0x00000002L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN		0x00000002L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK		0x00000010L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN			0x00000010L
#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK		0x00000f00L
#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK		0x00008000L
#define CRTC_GEN_CNTL__CRTC_ICON_EN			0x00008000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK			0x00010000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN			0x00010000L
#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK		0x00060000L
#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK		0x00700000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK		0x01000000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN			0x01000000L
#define CRTC_GEN_CNTL__CRTC_EN_MASK			0x02000000L
#define CRTC_GEN_CNTL__CRTC_EN				0x02000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK		0x04000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B		0x04000000L

/* CRTC2_GEN_CNTL */
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK		0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN		0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK		0x00000002L
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN		0x00000002L
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK	0x00000010L
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE		0x00000010L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK	0x00000020L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE		0x00000020L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK	0x00000040L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE		0x00000040L
#define CRTC2_GEN_CNTL__CRT2_ON_MASK			0x00000080L
#define CRTC2_GEN_CNTL__CRT2_ON				0x00000080L
#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK		0x00000f00L
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK		0x00008000L
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN			0x00008000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK		0x00010000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN			0x00010000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK		0x00700000L
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK		0x00800000L
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS		0x00800000L
#define CRTC2_GEN_CNTL__CRTC2_EN_MASK			0x02000000L
#define CRTC2_GEN_CNTL__CRTC2_EN			0x02000000L
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK	0x04000000L
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B		0x04000000L
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK		0x08000000L
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN			0x08000000L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK		0x10000000L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS			0x10000000L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK		0x20000000L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS			0x20000000L

/* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK_MASK			0x000000ffL
#define AGP_CNTL__HOLD_RD_FIFO_MASK			0x00000100L
#define AGP_CNTL__HOLD_RD_FIFO				0x00000100L
#define AGP_CNTL__HOLD_RQ_FIFO_MASK			0x00000200L
#define AGP_CNTL__HOLD_RQ_FIFO				0x00000200L
#define AGP_CNTL__EN_2X_STBB_MASK			0x00000400L
#define AGP_CNTL__EN_2X_STBB				0x00000400L
#define AGP_CNTL__FORCE_FULL_SBA_MASK			0x00000800L
#define AGP_CNTL__FORCE_FULL_SBA			0x00000800L
#define AGP_CNTL__SBA_DIS_MASK				0x00001000L
#define AGP_CNTL__SBA_DIS				0x00001000L
#define AGP_CNTL__AGP_REV_ID_MASK			0x00002000L
#define AGP_CNTL__AGP_REV_ID				0x00002000L
#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK		0x00004000L
#define AGP_CNTL__REG_CRIPPLE_AGP4X			0x00004000L
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK		0x00008000L
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X			0x00008000L
#define AGP_CNTL__FORCE_INT_VREF_MASK			0x00010000L
#define AGP_CNTL__FORCE_INT_VREF			0x00010000L
#define AGP_CNTL__PENDING_SLOTS_VAL_MASK		0x00060000L
#define AGP_CNTL__PENDING_SLOTS_SEL_MASK		0x00080000L
#define AGP_CNTL__PENDING_SLOTS_SEL			0x00080000L
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK		0x00100000L
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X			0x00100000L
#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK		0x00200000L
#define AGP_CNTL__DIS_QUEUED_GNT_FIX			0x00200000L
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK		0x00400000L
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET		0x00400000L
#define AGP_CNTL__EN_RBFCALM_MASK			0x00800000L
#define AGP_CNTL__EN_RBFCALM				0x00800000L
#define AGP_CNTL__FORCE_EXT_VREF_MASK			0x01000000L
#define AGP_CNTL__FORCE_EXT_VREF			0x01000000L
#define AGP_CNTL__DIS_RBF_MASK				0x02000000L
#define AGP_CNTL__DIS_RBF				0x02000000L
#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK		0x04000000L
#define AGP_CNTL__DELAY_FIRST_SBA_EN			0x04000000L
#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK		0x38000000L
#define AGP_CNTL__AGP_MISC_MASK				0xc0000000L

/* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK__SHIFT			0x00000000
#define AGP_CNTL__HOLD_RD_FIFO__SHIFT			0x00000008
#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT			0x00000009
#define AGP_CNTL__EN_2X_STBB__SHIFT			0x0000000a
#define AGP_CNTL__FORCE_FULL_SBA__SHIFT			0x0000000b
#define AGP_CNTL__SBA_DIS__SHIFT			0x0000000c
#define AGP_CNTL__AGP_REV_ID__SHIFT			0x0000000d
#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT		0x0000000e
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT		0x0000000f
#define AGP_CNTL__FORCE_INT_VREF__SHIFT			0x00000010
#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT		0x00000011
#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT		0x00000013
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT		0x00000014
#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT		0x00000015
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT	0x00000016
#define AGP_CNTL__EN_RBFCALM__SHIFT			0x00000017
#define AGP_CNTL__FORCE_EXT_VREF__SHIFT			0x00000018
#define AGP_CNTL__DIS_RBF__SHIFT			0x00000019
#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT		0x0000001a
#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT		0x0000001b
#define AGP_CNTL__AGP_MISC__SHIFT			0x0000001e

/* DISP_MISC_CNTL */
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK		0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP		0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK	0x00000002L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP		0x00000002L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK		0x00000004L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP		0x00000004L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK	0x00000010L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK		0x00000010L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK	0x00000020L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK		0x00000020L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK	0x00000040L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK		0x00000040L
#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK		0x00000300L
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK		0x00000400L
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN		0x00000400L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK	0x00001000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP		0x00001000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK	0x00008000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK		0x00008000L
#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK		0x00010000L
#define DISP_MISC_CNTL__SOFT_RESET_LVDS			0x00010000L
#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK		0x00020000L
#define DISP_MISC_CNTL__SOFT_RESET_TMDS			0x00020000L
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK	0x00040000L
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS		0x00040000L
#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK		0x00080000L
#define DISP_MISC_CNTL__SOFT_RESET_TV			0x00080000L
#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK	0x00f00000L
#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK	0x0f000000L
#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK	0xf0000000L

/* DISP_PWR_MAN */
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK	0x00000001L
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN		0x00000001L
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK	0x00000010L
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN		0x00000010L
#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK		0x00000300L
#define DISP_PWR_MAN__DISP_D3_RST_MASK			0x00010000L
#define DISP_PWR_MAN__DISP_D3_RST			0x00010000L
#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK		0x00020000L
#define DISP_PWR_MAN__DISP_D3_REG_RST			0x00020000L
#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK		0x00040000L
#define DISP_PWR_MAN__DISP_D3_GRPH_RST			0x00040000L
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK		0x00080000L
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST		0x00080000L
#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK		0x00100000L
#define DISP_PWR_MAN__DISP_D3_OV0_RST			0x00100000L
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK		0x00200000L
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST		0x00200000L
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK		0x00400000L
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST		0x00400000L
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK		0x00800000L
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST			0x00800000L
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK		0x01000000L
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST		0x01000000L
#define DISP_PWR_MAN__TV_ENABLE_RST_MASK		0x02000000L
#define DISP_PWR_MAN__TV_ENABLE_RST			0x02000000L
#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK		0x04000000L
#define DISP_PWR_MAN__AUTO_PWRUP_EN			0x04000000L

/* MC_IND_INDEX */
#define MC_IND_INDEX__MC_IND_ADDR_MASK			0x0000001fL
#define MC_IND_INDEX__MC_IND_WR_EN_MASK			0x00000100L
#define MC_IND_INDEX__MC_IND_WR_EN			0x00000100L

/* MC_IND_DATA */
#define MC_IND_DATA__MC_IND_DATA_MASK			0xffffffffL

/* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT		0x00000000
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT		0x00000001
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT	0x00000002
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT	0x00000003
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT		0x00000004
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT		0x00000005
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT	0x00000006
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT	0x00000007
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT		0x00000008
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT	0x00000009
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT	0x0000000a
#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT		0x0000000c
#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT		0x0000000e
#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT		0x00000010
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT		0x00000012
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT		0x00000014
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT	0x00000016
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT	0x00000017
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT		0x00000018
#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT		0x0000001a
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT		0x0000001c
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT	0x0000001e
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT	0x0000001f

/* MC_CHP_IO_CNTL_B1 */
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT		0x00000000
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT		0x00000001
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT	0x00000002
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT	0x00000003
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT		0x00000004
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT		0x00000005
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT	0x00000006
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT	0x00000007
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT		0x00000008
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT	0x00000009
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT	0x0000000a
#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT		0x0000000c
#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT		0x0000000e
#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT		0x00000010
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT		0x00000012
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT		0x00000014
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT	0x00000016
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT	0x00000017
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT		0x00000018
#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT		0x0000001a
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT		0x0000001c
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT	0x0000001e
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT	0x0000001f

/* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK		0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA		0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK		0x00000002L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA			0x00000002L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK		0x00000004L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA		0x00000004L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK		0x00000008L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA		0x00000008L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK		0x00000010L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA		0x00000010L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK		0x00000020L
#define